Hierarchical Codebook Design for Near-Field mmWave MIMO Communications Systems

In millimeter-wave communication, large antenna arrays are required to\nachieve high power gain by steering towards each other with narrow beams, which\nposes the problem to efficiently search the best beam direction in the angle\ndomain at both Tx and Rx sides. As the exhaustive search is time consuming,\nhierarchical search has been widely accepted to reduce the complexity, and its\nperformance is highly dependent on the codebook design. In this paper, we\npropose two basic criteria for the hierarchical codebook design, and devise an\nefficient hierarchical codebook by jointly exploiting sub-array and\ndeactivation (turning-off) antenna processing techniques, where closed-form\nexpressions are provided to generate the codebook. Performance evaluations are\nconducted under different system and channel models. Results show superiority\nof the proposed codebook over the existing alternatives.\n

As a hierarchical layout design method that can handle hierarchical designs of large‐scale integrated circuits, the BSG method, one of the general structural layout methods, is hierarchical and has evolved as a layout method including interconnections. It is the objective of this paper to construct a design system that will provide feedback as a guideline for circuit design modification in which the layers in the circuit design are faithfully represented and are evaluated from the point of view of layout, and the placement is reconstructed for optimization. Hierarchical BSG is realized by combining smaller BSGs (elemental BSGs) with root trees. The size, number, and hierarchical trees of BSGs can be specified by the designer. An experiment to demonstrate the hierarchical effect is carried out by artificially setting a hierarchical design environment with a combination of several thousands of cells. Performance competitive with that without a hierarchical approach is obtained in the resultant areas and interconnect lengths. As a layout algorithm, the number of rectangles to be treated is increased by one order of magnitude so that several tens of thousands of rectangles can be placed with high quality. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 85(3): 12–21, 2002

In this paper, we propose a hierarchical distributed design method of stabilizing controllers for an evolving network system where a part of the network system changes as installing a new dynamical system, which is called an evolving component. First, supposing that the dimension of the evolving network system is low enough to make the existing controller design methods applicable, we propose a design method of a stabilizing controller such that the whole evolving network system is kept to be stable as long as the evolving component does not spoil the local stability of the part of the evolving network system. Next, on the basis of this controller design, we propose a hierarchical distributed design method of stabilizing controllers for a large-scale evolving network system. The main idea of the hierarchical distributed design is to apply the proposed distributed design to evolving components that are hierarchically decomposed, thereby realizing a scalable handling of large-scale evolving network systems. Finally, we demonstrate the proposed method through an example of evolving power systems.

A Hierarchical Platform-Based Design (Hi-PBD) method is put forward for SoC system design. This method divides SoC system design flow into three levels (i.e. system model level, virtual components level and real components level) to achieve separation of function from structure and separation of computation from communication. HI-PBD defines two mapping processes (i.e. design planning and virtual-real synthesis) to go through all the three design levels. Hi-PBD supports reuse of both the three level design templates and the two mapping results, which increased reusing efficiency greatly. Besides, Hi-PBD boosts up design flexibility by means of supporting revision at all the three level and ensures the final design target satisfies performance requirements through a novel performance constraints transmission strategy. Experiments indicate Hi-PBD method improves SoC high level design efficiency by 30%-40%, and this method achieves platform template reuse ratio by 75%-90%.

A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21 K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design. >

New support vector-based design method for binary hierarchical classifiers for multi-class classification problems

Extremely large-scale antenna array (ELAA) is a common feature of several key candidate technologies for sixth generation (6G) mobile networks, such as ultra-massive multiple-input-multiple-output (UM-MIMO), cell-free massive MIMO, reconfigurable intelligent surface (RIS), and terahertz communications. Since the number of antennas is very large for ELAA, the electromagnetic radiation field needs to be modeled by near-field spherical waves, which differs from the conventional planar-wave-based radiation model of 5G massive MIMO. As a result, near-field MIMO communications will become essential in 6G wireless networks. In this article, we systematically investigate the emerging near-field communication techniques. First, we present the fundamentals of nearfield communications and the metric to determine the near-field ranges in typical communication scenarios. Then we investigate recent studies specific to near-field communications by classifying them into two categories: techniques addressing the challenges and those exploiting the potentials in near-field regions. Their principles, recent progress, pros, and cons are discussed. More importantly, several open problems and future research directions for near-field communications are pointed out. We believe that this article will inspire more innovations in this important research topic of near-field MIMO communications for 6G.

New paradigms in hierarchical porous scaffold design for tissue engineering

Current wireless power transfer (WPT) technology is widely used for various applications because of convenience and safety. One of the typical application of the WPT system is the near-field communication (NFC) system utilized mobile WPT system. However, WPT systems have problems with electromagnetic field (EMF) leakage which can cause electromagnetic interference (EMI) issues on the nearby electrical devices. In this paper, we propose the dual resonance NFC coil for EMF reduction. Proposed dual resonance coil generates resonance not only at the NFC operating frequency of 13.56 MHz but also at the wireless charging frequency 130 kHz. When comparing the proposed NFC coil with a typical NFC antenna, the total EMF level of the WPT system is reduced by 3.96 dB at 130 kHz without any effect at the NFC operating frequency of 13.56 MHz.

With the rapid advancement of sixth-generation (6G) network communication technology, improvements in data transmission rates, latency, and reliability have driven substantial growth in Internet of Vehicles (IoV) applications. Among these, the integration of 6G-enabled extremely large-scale antenna arrays (ELAAs) has extended the range of near-field (NF) communication, enabling their application in IoV to facilitate efficient and accurate environmental sensing. Through NF communication, vehicles can achieve high-accuracy localization and perception by analyzing the signal phase, channel state information, and beamforming calculations. However, positioning and sensing tasks place substantial computational and energy demands on edge devices, often exceeding traditional capacity limits. To address this challenge, task offloading has emerged as a solution, with mobile edge computing (MEC) offering a lower-latency alternative to centralized cloud computing by processing tasks at the network edge. Despite these advantages, MEC’s limited resources present challenges as the number of connected vehicles increases. Existing approaches to resource allocation often overlook the varied accuracy requirements of IoV tasks, where high-accuracy tasks like indoor navigation require stringent performance standards, while lower-accuracy tasks may tolerate reduced precision to save resources. Motivated by this, we propose an accuracy-based classification scheme for IoV positioning and sensing tasks, which dynamically adjusts accuracy requirements to reduce delay and energy consumption. Our approach maps total energy, accuracy loss, and delay to an overall quality of service (QoS) metric, and employs an optimization algorithm that leverages gradient descent and greedy strategies to balance resource allocation and accuracy selection. Extensive simulations demonstrate the effectiveness of the proposed scheme in reducing delay and energy consumption while maintaining high accuracy, significantly outperforming benchmark strategies.

Noise analysis for intra-body communication based on parasitic capacitance measurement

In design of a multistage machining process, process tolerance allocation at each stage and design of process layouts, in particular, the fixture layouts, should be optimized considering dimensional tolerance stackup or variation propagation. When multiple error sources contribute to the tolerance stackup, the dimensionality of the design space could be large and design solution may not be unique. One strategy is to prioritize the allocation of tolerances to different error sources at each stage through proper selection of cost functions. Considering the fact that the cost function selection can be very subjective and the knowledge regarding cost structures is very limited, we propose a hierarchical process design method using error equivalence concept to aggregate multiple error sources together. The main idea is to allocate tolerances to the aggregated error sources at each stage and then further distribute the tolerance to individual error sources through cost analysis. The advantage is two-fold: (1) limiting the impact of cost function selection within individual stages to avoid overhaul of process design caused by subtle change in cost functions, and (2) enabling the optimization of fixture layouts to reduce the overall tolerance stackup due to multiple error sources. To reduce computational load in optimizing process layouts, a computer experiment model is developed to explore a large number of process design alternatives. The robustness of the optimal tolerance is evaluated through sensitivity analysis, which provides guidance for process design. We illustrate the error-equivalence-based process design method by a multistage machining process. The results have shown that the proposed method could significantly reduce the design space and increase the design efficiency.

Kernel methods, specifically support vector machines (SVMs), have been widely used in many fields for data classification and pattern recognition. The performance of SVMs is mainly affected by kernel functions. With the growing interest of biological data prediction and chemical data prediction such as structure-property based molecule comparison, protein structure prediction and long DNA sequence comparison, more powerful and flexible kernels need to be designed in order effectively to express the prior knowledge and relationships within each data item. In this paper, the granular kernel concept is presented and related properties are described in detail. A hierarchical kernel design method is proposed to construct granular kernel trees (GKTs). For a particular problem, genetic algorithms (GAs) are used to find the optimum parameter settings of GKTs. In applications, SVMs with new kernel trees are employed for the comparisons of drug activities. The experimental results show that SVMs with GKTs and evolutionary GKTs can achieve better performances than SVMs with traditional RBF kernels in terms of prediction accuracy.

The popularity of the Near-Field Communication (NFC) system stems from being able to establish communication by merely being in the vicinity of another NFC device, an operation known as “tap and go”. An NFC device is quite complex: it has to support both ASK/BPSK modulation, variable data rates from 106kb/s to 848kb/s, different ASK modulation indices (8% to 100%), different card types (NFC-A/B/F), and various coding. It also has different operating modes such as Proximity-Inductively-Coupled Card (PICC) or card-emulation mode, Proximity-Coupled-Device (PCD) or reader mode and Peer-to-Peer (P2P) mode. Furthermore, some PCDs transmit NFC-A/B/F ASK data in a polling loop manner. Therefore, PICC receivers must support joint data-type detection for successful communication with such PCDs. The device shown in Fig. 9.1.1 supports all these operating modes and complies with ISO-14443, ISO-18092 and NFC Forum standards. The SoC has an ultra-low current receiver, a digital transmitter with a 250mA-maximum-current-drive Class-D PA, a Single-Wire Protocol (SWP) supporting two external UICC SIM cards and one micro-SD chip, an energy-harvesting rectifier unit, an agile synthesizer, and a digital modem. Traditionally, two separate receivers with respective synthesizers and clock recovery/generation circuits are adopted for PICC, PCD and P2P modes [1,2]. In addition, three parallel analog demodulators are needed (one each for NFC-A, B and F) to support joint data-type detection, thus increasing die area significantly. The focus of this paper is the adoption of a single receiver with one reconfigurable PLL to support all NFC modes for compact die area.

The near field communication (NFC) technology helps save both time and power when compared with Bluetooth and other similar technologies. However, NFC is vulnerable to various networking attacks such as message modification. In this work, a secure processing technique is introduced to protect the NFC devices and associated data from several attacks. A certificate record is added to the NFC Data Exchange Format (NDEF) message to enhance security. The proposed processing technique in a NFC system checks the authenticity of the sender, then if appropriate, processes the incoming NDEF messages and stores them in device memory. Using MATLAB, an NFC system with the proposed processing technique is simulated. Simulation results suggest that the processing time increases linearly as the certificate size increases and the processing time remains almost the same for various record sizes. It is also observed that the proposed protocol offers better security by detecting tag manipulation, certificate modification, etc. The proposed secure processing technique for NFC can be extended to enhance security in ubiquitous computing and mobile communication.