High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory

Multi-user technique is a method which allows a transmitter serves multiple users in the same time. In the Massive-MIMO, Multi-user technique could be implemented with the help of beamforming technique which allows the system to create several beams in the same time, where every beam serves a different user. In this paper, we introduce a method called Fair-Chordal Distance User Selection (Fair-CDUS) to equalize the user selection in Massive-MIMO System. The fairness level which is measured in this research is the frequency of user selection. In this paper, we also explain how to adjust the degree of the fairness with our proposed method.

To fully utilize the spatial multiplexing gains or array gains of massive MIMO, the channel state information must be obtained at the transmitter side (CSIT). However, conventional CSIT estimation approaches are not suitable for FDD massive MIMO systems because of the overwhelming training and feedback overhead. In this paper, we consider multi-user massive MIMO systems and deploy the compressive sensing (CS) technique to reduce the training as well as the feedback overhead in the CSIT estimation. The multi-user massive MIMO systems exhibits a hidden joint sparsity structure in the user channel matrices due to the shared local scatterers in the physical propagation environment. As such, instead of naively applying the conventional CS to the CSIT estimation, we propose a distributed compressive CSIT estimation scheme so that the compressed measurements are observed at the users locally, while the CSIT recovery is performed at the base station jointly. A joint orthogonal matching pursuit recovery algorithm is proposed to perform the CSIT recovery, with the capability of exploiting the hidden joint sparsity in the user channel matrices. We analyze the obtained CSIT quality in terms of the normalized mean absolute error, and through the closed-form expressions, we obtain simple insights into how the joint channel sparsity can be exploited to improve the CSIT recovery performance.

In this paper, we develop the weighted sum-rate maximization (WSRM) problem for the cooperative multicell multiuser massive MIMO (C4M) system with the limited cooperative scheme where each base station (BS) has user data of all the users in a system. It is shown that by the simple domain change technique, the WSRM problem can be exploited for hidden mono-tonicity and turn out to be a monotonic optimization problem. We propose a robust algorithm for discretized approximation of the Pareto boundary of achievable rate region. Using this algorithm, the normal boundary intersection (NBI) problem is solved. We solve the WSRM problem by using the outer polyblock approximation (OPA) algorithm. Through simulation results, we show that our proposed method has high accuracy as well as a fast convergence rate.

A multiuser massive MIMO system with mutual coupling is investigated in finite-dimensional channel scenarios. The uplink ergodic achievable rate is analytically derived for a multiuser massive MIMO system equipped with a rectangular planar uniform antenna array at the base station (BS). Numerical results show that the mutual coupling effect reduces the uplink achievable rate of multiuser massive MIMO systems when the antenna distance decreases. But when the size of the antenna array is fixed, the uplink achievable rate increases with the growing of antenna number.

Deep learning models are generally trained using a single-precision floating-point number system. However, in the inference process, they use simpler number systems like integers and fixed-points, because of their small design area and low power consumption, despite the accuracy loss and quantization parameter overhead due to their quantization. In general, a floating-point MAC unit makes it unsuitable for inference engines and especially for the area, power, and heat-sensitive devices such as Processor-In-Memory (PIM). In this paper, we propose an efficient MAC design based on the bfloat16 suitable for neural network operations while considering the characteristics of data used for deep learning. Our techniques simplified the design by removing the circuits for handling an underflow, an overflow, and a normalization from the critical path and treating them as exceptions. Also, we improved the computational accuracy by extending the bit-width of the mantissa inside the MAC unit and eliminated unnecessary normalization at every computation. Compared with a MAC unit without our optimization by using the Samsung 65nm library, we reduced the delay of a non-pipelined MAC unit by 47.3%, the area by 9.1 %, and the power consumption by 24.2%, respectively. Furthermore, we show that the proposed bfloat16 MAC outperformed the 16-bit integer MAC in terms of area and power consumption. We also show the design of a 1GHz 3-stage pipelined MAC unit with its performance analysis.

This work focuses on the multi-cell multi-user distributed massive MIMO (DM-MIMO) systems, of which each user is equipped with single antenna and the base stations (BSs) consists of distributed antenna units. We first investigate the arbitrary BS antenna topology scenario. The derivation indicates that in this case the achievable uplink rate of an arbitrary user in central cell depends on both the number of BS's antennas and the users' access distance to each distributed antenna unit (DAU). As a result, the performance analysis based on the derivations is difficult. To overcome this issue and achieve clearer insight, we then consider a circularly distributed BS antenna array and obtain the asymptotic uplink rate of an arbitrary user by considering the asymptotic case where the number of antennas of BSs tends to infinity. It is achieved that the asymptotic uplink rate only depends on the distance from users' position to the center of reference cell. The presented numerical results show clearly that the distributed massive MIMO systems outperform the centralized ones. Moreover, it is also achieved that the interference from the adjacent cells imposes great impact on system performance. Besides this, in numerical analysis the average asymptotic uplink rate of a user is presented, which is free of the users' position and only depends on the radius of circular antenna arrays. It is achieved the maximum average uplink rate would be achieved when the radius of circularly distributed antenna array goes to its optimization location.

In this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders are not merged and the results are kept in double carry-save format where extra redundancy reduces critical path delay. Designed MAC units have 16×16-bit multiplier with 40-digit accumulate output for recursive multiply-add operations. The designs are synthesized on Altera <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> Stratix III FPGAs and provide superior performance compared to conventional pipelined carry-propagate multiply-accumulate units. The fusion in the arithmetic structure provides best performance compared to conventional pipelined multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic based MAC structures as well.

In this paper, a hybrid multi-user massive MIMO system operating on the mmWave frequency is considered. To reduce the heavy beam training overhead for such a massive MIMO system, we propose a 3D beam training algorithm, which estimates the azimuth and elevation of the angle of arrival (AoA) and departure (AoD) between the base station (BS) and the mobile stations (MSs). The proposed algorithm first executes a hierarchical search to acquire the range of azimuth and elevation, then applies an exhaustive search within this range for a more precise matching. Through this two-stage approach, the beam training overhead can be substantially reduced.

We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial-product generation circuitry and a reduction tree, while the second stage, thanks to a special sign-extension solution, implements all other functionality. Place-and-route evaluations using a 65-nm 1.1-V cell library show that the proposed architecture offers a 31% improvement in speed and a 32% reduction in energy per operation, averaged across operand sizes of 16, 32, 48, and 64 bits, over a reference two-cycle MAC architecture that employs a multiplier in the first stage and an accumulator in the second. When operating the proposed architecture at the lower frequency of the reference architecture the available timing slack can be used to downsize gates, resulting in a 52% reduction in energy compared to the reference. We extend the new architecture to create a versatile double-throughput MAC (DTMAC) unit that efficiently performs either multiply-accumulate or multiply operations for N-bit, 1 × N/2-bit, or 2 × N/2-bit operands. In comparison to a fixed-function 32-bit MAC unit, 16-bit multiply-accumulate operations can be executed with 67% higher energy efficiency on a 32-bit DTMAC unit. © 2006 IEEE.

Massive MIMO technology is a promising candidate for the next generation wireless communication systems. The basic idea is to implement a large number of antennas at the base station (BS) of a cell to serve a relatively small number of users. Such an approach brings many benefits in terms of the throughput and energy efficiency. Two major challenges associated with massive MIMO systems are high power consumption and high system complexity. These problems can effectively be dealt with by performing antenna-subset selection at the BS. In this paper, we propose low-complexity antenna-subset selection schemes for both single-cell and multiple-cell cooperative massive MIMO systems for equal-rate zero-forcing beamforming transmission at the BS. These schemes sequentially select an antenna that contributes the most to the overall system sum rate. Simulation results show that our proposed schemes outperform other schemes with similar computational complexities and even surpass some of the higher computational complexity schemes in a massive MIMO setting.

This paper illustrates the implementation of Multiply-Accumulate unit (MAC) to improve performance using the Ancient Indian Vedic Mathematics. Real-time signal processing needs high speed and high yield Multiplier-Accumulator (MAC) unit that consumes less power, which is always a key to achieve a high performance digital signal processing system. Speed of the multiplier is essential to MAC unit. Vedic Mathematics is the ancient mathematics. There are sixteenth unique sutras in the Vedic mathematics. The Sutras saves effort and time required in solving the problems as compared to the formal methods. The Sutra “Urdhav Triyagbhyam” (Vertical and Crosswise) is used inside the MAC unit as a multiplier. The coding is done in VHDL, synthesis is done in Xilinx ISE series and the FPGA synthesis is done using Xilinx Spartan library. The results show that design of MAC unit using Vedic multiplication is much more efficient in terms of delay and speed compared to conventional multiplication.

Wearable real-time Electrocardiogram (ECG) monitoring is an emerging wireless technology enabling early diagnosis and increased ability of prevention of cardiovascular diseases. However, the ECG signal suffers from Powerline Interference (PLI) which corrupts the biomedical recordings. Low power and high speed filtering of the ECG signal is essential to make the monitoring device portable. This paper proposes an FIR (Finite Impulse Response) filter based on Multiply-Accumulator (MAC) Unit to suppress the PLI noise. The performance of this filter largely depends on the speed and power of the MAC unit employed inside the filter. The current work compares various MAC units on Power, Performance and Area (PPA) benchmarks. It is shown that Booth-Wallace-Carry Look Ahead adder(CLA) based MAC is optimised for both timing and power which shows 6.2% improvement in performance and 12.1% reduction in power from other implemented designs. Thus, the real-time low power FIR filter is realised using Booth-Wallace-CLA MAC. The convergence time of the algorithm is observed to be less than 0.2 μsec with significant power savings to improve battery life.

In this article, we demonstrated a high-throughput gate-level-pipelined 8-bit multiply-accumulate (MAC) unit with a long feedback loop using low-voltage rapid single-flux quantum (LV-RSFQ) logic. The long feedback loop in the MAC unit is an obstacle for high-throughput operation because the logic gates must wait for the delayed inputs from the feedback loop. The LV-RSFQ logic makes high-frequency operation even more difficult by larger and more variable feedback delay. We design the feedback loop by using counter-flow clocking and adding many D flip-flops to divide the long feedback loop into shorter paths. The target clock frequency of the MAC unit with a feedback loop was set to 30 GHz by the experimental results of the MAC unit without a feedback loop. We model the clock frequency and its circuit overhead in a feedback loop to design the feedback loop in the MAC unit achieving 30 GHz with a minimum overhead. The test chips are fabricated using the national institute of advanced industrial science and technology (AIST) 10-kA/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{^{2}}$</tex-math></inline-formula> Advanced Process 2. We have successfully obtained high-throughput 30-GHz operations in the LV-RSFQ MAC unit with a long feedback loop by using the model-based design. The maximum operating frequency of the MAC unit reaches 40 GHz.

We consider the impact of transceiver power consumption on the energy efficiency (EE) of the zero-forcing (ZF) detector in the uplink of massive MIMO systems, where a base station (BS) with M antennas communicates coherently with K single antenna user terminals (UTs). We consider the problem of maximizing the EE with respect to (M, K) for a fixed sum spectral efficiency. Through analysis, we study the impact of system parameters on the optimal EE. System parameters consists of the average channel gain to the users and the power consumption parameters (PCPs) (e.g., power consumed by each RF antenna/ receiver at BS). When the average user channel gain is high or else the BS/UT design is power inefficient, our analysis reveals that it is optimal to have a few BS antennas and a single user, i.e., nonmassive MIMO regime. Similarly, when the channel gain is small or else the BS/UT design is power efficient, it is optimal to have a larger (M, K), i.e., massive MIMO regime. Tight analytical bounds on the optimal EE are proposed for both these regimes. The impact of the system parameters on the optimal EE is studied, and several interesting insights are drawn.

This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-/spl mu/m double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance.