High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares

With the growing threat of the side-channel attack (SCA) to the cryptographic algorithm’s implementations, the masking method has become one of the most promising SCA countermeasures for securely implementing, for example, block ciphers. The basic principle of the masking method is that if the sensitive variable (which, by definition, depends on sensitive information) is split into some random variables and they are manipulated in a secure manner, then the relationship between the random variables and the corresponding side-channel information may look independent from the outside world. However, after the introduction of the glitch attack, there has been a lot of concern about the security of the masking method itself. And, to mitigate the threat of the glitch attack, the threshold implementation (TI) and G-equivariant gates were independently introduced as countermeasures. In this paper, we consider the main notions of two such independent glitch attack’s countermeasures, say, non-completeness and G-equivariance, and investigate their relationship. The contribution of this paper is three-fold. First, we show that the widely-circulated proof that the non-complete TI with uniform inputs guarantees the security against the 1st order DPA even in the presence of glitches is not satisfactory. Next, using the extended notion of G-equivariance to the higher-order setting, we prove that non-completeness implies G-equivariance, which, in turn, means that the non-complete TI with uniform inputs has resistance against the glitch attack. Thirdly, we prove that the set of non-complete gates is a proper subset of the set of G-equivariant gates by showing there is a gate that is G-equivariant but not non-complete.

Side-channel attacks, particularly differential power analysis (DPA) attacks, are efficient ways to extract secret keys of the attacked devices by leaked physical information. To resist DPA attacks, hiding and masking methods are commonly used, but it usually resulted in high area overhead and performance degradation. In this brief, a DPA countermeasure circuit based on digital controlled ring oscillators is presented to efficiently resist the first-order DPA attack. The implementation of the critical S-box of the advanced encryption standard (AES) algorithm shows that the area overhead of a single S-box is about 19% without any extra delay in the critical path. Moreover, the countermeasure circuit can be mounted onto different S-box implementations based on composite field or look-up table (LUT). Based on our approach, a DPA-resistant AES chip can be proposed to maintain the same throughput with less than 2K extra gates.

Cryptography is securing information using mathematical techniques like encryption and decryption. Cryptanalysis uses side-channel attacks to undermine security. The efficient type of power analysis of the side channel and Differential Power Analysis (DPA) statistically assesses the power use of the cryptographic method and provides private details. This paper proposes the design of a Compact PRESENT S-box (CPSB), using Three-Phase Dual Rail Pre-Charge Logic (TDPL) combined with Charge Balancing Symmetric Pre-Resolve Adiabatic Logic (CBSPAL). The primary contribution of this research lies in the development of a power-efficient logic style that improves the performance of the S-box while maintaining conflict against DPA attacks. By employing TDPL, the design achieves consistent power consumption across various input configurations, thereby mitigating the risk of side-channel attacks. The focus of this work is to propose an innovative implementation approach rather than the security aspects of cryptography itself. The proposed methodology proves a substantial reduction in power overhead and area, making it suitable for resource-constrained environments, like Internet of Things (IoT) applications. A correlation study is carried out to calculate the Compact Present S-box implementation's DPA resistance characteristic. The power traces are examined. The proposed design makes power consumption consistent and decreases area and power overhead by 15.3% and 13.6%, respectively. Performance indicators for the security are NED, NSD, and Pearson correlation coefficient. The connection is the same for all conceivable input and key pairings. When compared with other designs, the NED and NSD were determined to be 0.02% and 0.01%, respectively.

SEED, the Korean standard block cipher algorithm, is a 128-bit symmetric key block cipher algorithm. Although SEED is theoretically safe, cryptographic devices with SEED modules are vulnerable to differential power analysis due to leakage information. Recently, differential power analysis has been widely researched, and various countermeasure techniques against differential power analysis have been proposed. In this paper, we embodied SEED hardware modules with differential power analysis countermeasure techniques using masking methods, and we generated random number using simple PRNG module. We embodied the SEED hardware modules using VHDL, and analyzed the result of simulation and synthesis. ??2010 IEEE.

Authenticated ciphers are designed to provide two security requirements simultaneously, i.e. confidentiality and integrity. The CAESAR competition was ended with introducing six authenticated ciphers for several applications as the winners. The OCB and COLM authenticated ciphers are two AES-based winners, respectively for high-speed and defense in-depth applications. Similar to the implementation of any other cryptographic algorithm, unprotected implementations of these ciphers could also be vulnerable to side-channel attacks, especially differential power analysis (DPA). In this work, first, the OCB and COLM ciphers are implemented on FPGA of SAKURA-G board. Then their vulnerability is shown with power leakage detection using t-test over the power traces. Also, the first-order protected version of these ciphers is presented using two masking scheme, i.e. threshold implementation (TI) and domain-oriented masking (DOM). To verify these countermeasures, the first and second-order t-test is conducted, to indicate the resistance of protected schemes to the first-order DPA attacks. Finally, the hardware implementation of two protected and unprotected versions of ciphers on FPGA are benchmarked based on the criteria of area, maximum frequency, and throughput. Additionally, the ratio of the increased area and decreased throughput to the unprotected ciphers have been compared with previous works.

In recent years, power analysis attacks have caused increasingly serious security threats on cryptographicalgorithm, to solve this problem different researcher has put forward many solutions, and among them the fixed value masking technology is one of the mostly used due to its lower cost and faster speed. Both theoretical and practical results have shown that the masking method has a good resistance to differential power analysis (DPA) attack. So based on the in-depth study of fixed masking technology, this paper proposed a second order DPA attack (SODPA) with the help of a pre-processing treatment. In the end, we implemented this attack on a fixed value masked AES encryption algorithm running in Mega16. The experimental result shows that, if the mask value is unknown, ordinary DPA cannot recover the right key, while the second order DPA only needs about 500 power curves to get the correct key. In the meantime, the differences between right and wrong keys are very obvious, which strongly proved the validity and practicability of our method.

Cryptographic implementation is one of the vital applications for FPGAs with security as its major standpoint. But it still requires a lot of efforts to keep it aloof from attacks like Side Channel Attacks (SCA). One of the major attacks that threaten the security of FPGA implementation of cryptographic algorithm is Differential Power Analysis (DPA). In this paper, we have discussed various approaches to defend against DPAs. These new programs suggested in the different approaches with some results aid in evenly distributing the power consumption in FPGAs making it less prone to DPAs.

On two DES implementations secure against differential power analysis in smart-cards

Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with constant power dissipation have been widely used. However, the right use of such circuits for secure applications needs not only a fully symmetric structure, but also removing any memory effect that could leak information. We propose an improved memory-less fully symmetric Xor/Xnor pull-down logic configuration, to be used with any differential technique, for immediate application in crypto-graphic secure applications.

The additional information (side effects) in Elliptic Curve Cryptography (ECC) hardware can be used to attack cryptographic systems. Additional information related to time, power consumption and electromagnetic radiation. Side channel attacks have been done with SPA (Simple Power Analysis), DPA (Differential Power Analysis), SEMA (Simple Electromagnetic Analysis) and DEMA (Differential Electromagnetic Analysis). Some scalar multiplication algorithm can be used to countermeasure SPA attack on elliptic curve cryptography. In this study, conducted experiments side-channel attacks ECC hardware implementations use binary algorithms by observing power consumption of ECC processor on FPGA. Experimental of side-channel attack is conducted to guess the secret key for data encryption and decryption by looking at the physical differences on hardware side effects. In this study, side-channel attack experimental is successful 100% get the key by analyzing of power consumption ECC processor.

Security in embedded systems is of critical importance since most of our secure transactions are currently made via credit cards or mobile phones. Power analysis-based side channel attacks have been proved as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks on public key cryptographic algorithms, such as elliptic curve cryptography, mostly in software, hinder performance and repeatedly attacked using improved techniques. To protect these public key ciphers from both simple power analysis and differential power analysis, as a hardware solution, we propose to take advantage of the inherent parallelisation capability in multi-modulo residue number systems (RNS) architectures to obfuscate the secure information. Random selection of moduli is proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, although still providing all the benefits of RNS. In this study, the authors show that differential power analysis, cross correlation analysis and correlation power analysis for a simple binary double-and-add operation are thwarted using their solution.

SUMMARY Recently, side-channel attacks have become a serious problem. These attacks estimate the secret keys of cryptography circuits embedded in hardware. In particular, the most threatening side-channel attacks are differential power analysis and correlation power analysis, which use the correlation between information processing and power consumption, which are related to secret keys in cryptography circuits. Therefore, new measures are required to prevent confidential information in cryptography circuits from being leaked to side-channel information, such as power consumption. When designing preventive measures, resistance to side-channel attacks, for instance tamper resistance, must be evaluated. This study proposes a new simulation method by which tamper resistance can be verified in the algorithm and architecture design phases. Experimental results show the validity of the proposed simulation method. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(2): 40–51, 2014; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22342

Side channel analysis(SCA) focuses on attacking cryptographic algorithm implementations by collecting leaked information and analyzing the correlation between the leaked and key information in the cryptographic system. Currently, SCA is the main threat to cryptographic implementations, with DPA (differential power analysis) and DFA (differential fault analysis) being two of the most threatening types of SCA. However, the existing countermeasures against DPA and DFA have shortcomings and can hardly protect cipher designs perfectly. Based on a comprehensive analysis of DPA and DFA, this paper proposes a new idea of using an evolutionary cipher (EVOC) against DPAs based on the model proposed by Kocher, and several different new types of DFAs. In fact, an EVOC is a kind of dynamic cipher designing method. Moreover, combined with intelligent searching algorithms and cryptography design policies, EVOCs utilize the dynamic and unpredictable properties of TRNG (a truly random number generator) to ensure cipher design at a high level of security. Therefore, with an EVOC we could design cryptography algorithms with high security to resist mathematical analysis as well as DPAs and DFAs. This paper analyzes and proves the security, efficiency, cost, and original features of EVOCs against DPA and DFA both theoretically and experimentally. Compared with existing countermeasures against SCAs, EVOCs use dynamic non-linear operations to destroy the bases of DPA and DFA. At the algorithm level, EVOCs are more efficient than other resistance methods. Based on the theory and experiments, this paper proposes certain modifications to the EVOC in the AES (advanced encryption standard) algorithm, which can be referenced by other dynamic designs of cryptographic algorithms.

In order to protect a cryptographic algorithm against Power Analysis attacks, a well-known method consists in hiding all the internal data with randomly chosen masks.Following this idea, an AES implementation can be protected against Differential Power Analysis (DPA) by the “Transformed Masking Method”, proposed by Akkar and Giraud at CHES’2001, requiring two distinct masks. At CHES’2002, Trichina, De Seta and Germani suggested the use of a single mask to improve the performances of the protected implementation. We show here that their countermeasure can still be defeated by usual first-order DPA techniques.In another direction, Akkar and Goubin introduced at FSE’2003 a new countermeasure for protecting secret-key cryptographic algorithms against high-order differential power analysis (HO-DPA). As particular case, the “Unique Masking Method” is particularly well suited to the protection of DES implementations. However, we prove in this paper that this method is not sufficient, by exhibiting a (first-order) enhanced differential power analysis attack. We also show how to avoid this new attack.KeywordsTamper-resistant devicesSide-Channel attacksPower AnalysisDPATransformed Masking MethodUnique Masking MethodDESAES

Embedded systems are increasingly providing secure functionalities, which often rely on some dedicated hardware for symmetric and public-key cryptography. When resources are limited, elliptic curve cryptography (ECC) may be chosen instead of the more widely known RSA, which needs much longer keys for the same security level. However, ECC may be vulnerable, as any other cryptographic implementation, to side channel analysis, which may reveal secret information by analyzing collateral sources of information, such as power consumption. Countermeasures must be thus adopted at the design level, in order to ensure robust and secure operation of the device. We propose here a new scalar multiplication algorithm on an elliptic curve, based on a novel randomized window method. This design is protected against side channel attacks (Timing, Simple and Differential Power Analysis) and it is implemented over prime fields, but it can be applied to binary fields as well. In order to evaluate this countermeasure, we provide its costs, and an estimation of the additional entropy added to the computation against side channels attacks.