High performance 5 : 2 compressor architectures

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

The structure of modified tree multipliers with different adders is presented. Multiplication is an important fundamental arithmetic operation in all microprocessor circuits and algorithms. Currently the speed of multipliers is limited by the speed of adders used for partial products addition. In this paper Conventional Array Multiplier and Dadda Multiplier are compared with the Wallace multiplier in terms of delay. Further a proposed sixteen bit Wallace multiplier is implemented by using Carry Select Adder (CSLA) and Binary to Excess −1 Converter (BEC) adder. The delay for Wallace multiplier using CSLA is less when compared to Wallace multiplier with BEC. These multipliers are coded in Verilog HDL, simulated and synthesized by using XILINX software 12.2 on Spartan 3E FPGA device xc3s500–5fg320.

Troposcatter propagation delay is one of the most significant sources of errors in troposcatter time comparison. The existing methods of calculating troposcatter propagation delay face problems in terms of effectively reflecting the influence of the meteorological environment on troposcatter propagation delay, due to the insufficient spatial and temporal resolution of the meteorological data. This article proposes a high-precision calculation method for troposcatter propagation delay based on atmospheric reanalysis data. The troposcatter propagation path and the refractive index along the troposcatter data were obtained by combining 3D ray tracing with the European Centre for Medium-Range Weather Forecasts’ Reanalysis 5 (ERA5), with high spatial and temporal resolution. This found the hour-level time delay in troposcatter. The geometric delay, path delay, and total propagation delay of the troposcatter were calculated and analyzed via 12 scattering links in 6 typical geographical regions. It was found that the path delay was the main cause of the propagation delay of troposcatter, and that the proportion of geometric delay in the total propagation delay increased along with an increase in link distance. The propagation delay changed noticeably in different seasons. The path delay was higher in summer and lower in winter, the geometric delay was lower in summer and higher in winter, and the total propagation delay was mainly high in summer and low in winter. There were differences in delay date, seasonal fluctuation amplitude, and in hourly fluctuation standard deviation among different geographic areas.

CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> /W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As channel with width ratio (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> /W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> .

Multipliers play an important role in any processor or computing machine. The performance of arithmetic circuits is evaluated from the performance of multipliers of those circuits. The conventional multiplier circuits process only two binary data at a time for multiplication. This paper proposes a methodology to multiply three binary numbers at once. This methodology reduces the complexity of the circuit for multiplying three binary numbers as compared to the existing methods of multiplying. When implemented in a circuit, this has turned out to increase the performance of the multiplier based on proposed methodology in terms of power, gates and delay as compared to existing multipliers. Based on simulation results for design of circuit for multiplying three 4-bit binary numbers, the proposed methodology shows a reduction of 37.56, 62.90 and 41.35% in propagation delay, power consumption and gate counts, respectively, as compared to existing techniques.

In this paper, a high performance and reconfigurable MAC Array (HIPERMA) processor is designed for Synthetic Aperture Radar (SAR) systems. HIPERMA is composed of many coarse-grained reconfigurable units and can be configured to finish the algorithms based on matrix multiplication level. The processor maintains the performance of ASIC devices and flexibility of DSP, and also has inherent advantages over FPGA in terms of delay, area and configuration time. The measurement result shows it has a peak performance up to 20,000 MMACS based on SMIC 0.18 urn six-metal CMOS process.

Speed is an integral part of circuit designing. Conventional CMOS (C-CMOS) is one of the widely used logic style; however, it has the disadvantage of producing greater delay. Several alternatives have been proposed. One such alternative is the hybrid adders that provide better performance in terms of delay. Various hybrid adders have been proposed, for instance Transmission gate full adders (TGA) and Hybrid pass logic with static CMOS output drive (New HPSC), that provide different delays. In this research work, the performance comparison analysis of different adders is presented by observing its propagation delay and transistor count. The C-CMOS, TGA and New HPSC full adders were considered for the performance comparison. The circuits have been implemented in FINFET model with 32nm technology node and in MOSFET model with 180nm technology node. The circuit implementation and analysis are performed using Cadence^&#x00AE; Virtuoso tool. Simulation results reveal that TGA is relatively faster and requires minimum hardware than the other adders

1. A novel approach for analyzing transients in passive structures called "the method of moments" is introduced. It provides, as a special case, an analytic method for calculating the time delay and speed of propagation of electrical signals in any passive dendritic tree without the need for numerical simulations. 2. Total dendritic delay (TD) between two points (y, x) is defined as the difference between the centroid (the center of gravity) of the transient current input, I, at point y[tI(y)] and the centroid of the transient voltage response, V, at point x [tV(x)]. The TD measured at the input points is nonzero and is called the local delay (LD). Propagation delay, PD(y, x), is then defined as TD(y, x)--LD(y) whereas the net dendritic delay, NDD(y, 0), of an input point, y, is defined as TD(y, 0) - LD(0), where 0 is the target point, typically the soma. The signal velocity at a point x0 in the tree, theta(x0), is defined as [1/(dtv(x)/dx)[x = x0. 3. With the use of these definitions, several properties of dendritic delay exist. First, the delay between any two points in a given tree is independent of the properties (shape and duration) of the transient current input. Second, the velocity of the signal at any given point (y) in a given direction from (y) does not depend on the morphology of the tree "behind" the signal, and of the input location. Third, TD(y, x) = TD(x, y), for any two points, x, y. 4. Two additional properties are useful for efficiently calculating delays in arbitrary passive trees. 1) The subtrees connected at the ends of any dendritic segment can each be functionally lumped into an equivalent isopotential R-C compartment. 2) The local delay at any given point (y) in a tree is the mean of the local delays of the separate structures (subtrees) connected at y, weighted by the relative input conductance of the corresponding subtrees. 5. Because the definitions for delays utilize difference between centroids, the local delay and the total delay can be interpreted as measures for the time window in which synaptic inputs affect the voltage response at a target/decision point. Large LD or TD is closely associated with a relatively wide time window, whereas small LD or TD imply that inputs have to be well synchronized to affect the decision point. The net dendritic delay may be interpreted as the cost (in terms of delay) of moving a synapse away from the target point.(ABSTRACT TRUNCATED AT 400 WORDS)

Digital Signal Processor (DSP) as well as other microcontroller applications requires fast and low power consumption systems to compete with the advanced technology. The performance of the DSP applications mainly depends on the multiplier, because the multiplication requires more iterations, long time and large area of the system than other computations. Hence to improve the performance of the system it is required to have high speed and low power consumption multiplier. In this paper we proposed the comparative study of two different algorithms, first one is the conventional method called as “Booth Multiplier” and other is the vedic method “Nikhilam Navatascaram Dasatah” using reversible logic gates. Both the multipliers are designed and implemented by using Xilinx 13.2 ISE simulator. Comparative results of both the multipliers are analyzed in terms of delay, area and power consumption.

The wireless network environment in the future is going to include various heterogeneous wireless networks. In a heterogeneous wireless network environment, vertical handoff processes caused by the movement of users are inevitable. However, the research related to how to achieve seamless vertical handoff and improve QoS guarantees in today's heterogeneous wireless networks is still something to work on. Therefore, this paper proposed the Advanced Vertical Handoff Translation Center (Advanced VHTC) architecture for Wi-Fi/WiMAX heterogeneous wireless networks, aiming to improve the quality of services in heterogeneous wireless networks by means of packet formats translation between heterogeneous wireless networks and the MIH-based seamless vertical handoff mechanism, which cut down the time for vertical handoff and obtain high quality and persistent connection service. Lastly, with the brilliant results of a complete simulation, this paper will show the performance in terms of delay, jitter, packets loss and throughput to prove that the Advanced VHTC for next generation heterogeneous wireless networks can provide good QoS guarantees and obtain persistent transmission with high performance while performing seamless vertical handoff.

Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high voltage to provide high performance and at near-/sub-threshold voltage to provide ultra-low energy consumption.This paper studies different non-hybrid and hybrid SRAM L1 cache designs using several SRAM cell types and compare them in terms of delay, dynamic energy, leakage power and area.

Addition is an indispensable operation for any high speed digital system, digital signal processing or control system. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. In this work technology independent logic optimization is used to design 1-bit full adder with 20 different Boolean expressions and its performance is analyzed in terms of transistor count, delay and power dissipation using Tanner EDA with TSMC MOSIS 250nm technology. All the Boolean expressions are realized in terms of CMOS logic. From the analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.

Time-based medium access control (MAC) has potential advantages over FDMA and CDMA approaches in terms of hardware simplicity, energy efficiency, and delay. Unfortunately, the channel utilization of existing TDMA and CSMA acoustic MAC protocols is generally low due to the long propagation delays of acoustic signals. In this work, we argue that several ideas taken from RF protocols, including exclusive channel access, are either unnecessary in acoustic networks or must be redefined. We present and evaluate UW-FLASHR, a time-based MAC protocol which does not require centralized control, tight clock synchronization, or accurate propagation delay estimation. We demonstrate that UW-FLASHR can achieve significantly higher channel utilization than the maximum utilization possible with existing time-based exclusive access MAC protocols, particularly when the ratio of propagation delay to transmission delay is high or data payloads are small.

As a product of the combination of computer network technology and database technology, distributed database system has the characteristics of independence and transparency, centralized node combination, replication transparency and easy expansion. However, due to its complex access structure, distributed database system naturally has a high demand for query optimization. This paper proposes a high-performance data processing method between distributed database and multi-core processors based on PSO (Particle Swarm Optimization) to solve the task scheduling problem between multi-core processors. Inertia weight is introduced, which is added to the speed of particle flight to adjust the global and local search ability of stationary particles. The research results show that this method reduces the error rate of database query, and the overall performance of database query method is better. The improved PSO algorithm improves the searching ability of particles by dynamically adjusting the inertia weight. Therefore, the improved PSO is a high-performance algorithm to solve the real-time task scheduling problem of multi-core processors.

In the big data processing systems, the amount of data is increasing. At the same time, the real-time requirement of data processing and analysis is higher and higher. Therefore, it is required that the big data processing and analysis systems have better performance. Job scheduling plays an important role in improving the overall system performance in big data processing frameworks. However, job scheduling is a difficult NP-hard problem. There are many factors that need to be considered for job scheduling. For example, jobs have dependencies among stages, therefore we should not allocate resources to tasks that are not ready. Sometimes, there are constraints between jobs. These are a challenge to the scheduling performance of big data processing and analysis systems. In this paper, we try to solve the problem by translating it into Boolean Satisfiability Problem (SAT) which is an exact method. SAT-based scheduling algorithm is not a new approach, but in the past it mainly used to solve the static scheduling problems. For dynamic scheduling system, it requires all problems to be solved within a limited time, which is a challenge for SAT encoding. In this paper, we refer to the previous SAT solution to the Job Shop Scheduling Problem, and adjust the algorithm to meet the requirements of the big data processing system. At the same time, we optimized the coding approach and reduced the number of clauses. Thus, the efficiency of the problem solved is improved to meet the performance requirements. The experimental results show that the number of clauses is reduced by more than 30%, and the processing time of the SAT solver to get the solution can be reduced by more than 50%. To demonstrate its effectiveness, we have also implemented our new job scheduler in Apache Hadoop YARN, and validated its effectiveness