High Performance CMOS Voltage Level Shifters Design for Low Voltage Applications

This paper describes architecture of voltage level shifter used in multi-supply design applications and an application of voltage level shifter. Voltage level shifter is a device which converts one voltage level to another. Voltage level shifters are used to interface various circuit blocks operating at different supply voltages. At the boundaries of different voltage islands on the system-on-chip (SoC) voltage level shifter is used. The proposed voltage level shifter converts low input voltage level into high level voltage output with increased speed and much less power consumption. The architecture is designed with multi-threshold voltage CMOS technique. The multi-threshold voltage CMOS technique is used in the design of voltage level shifter in order to reduce delay and power. Low-threshold voltage devices are used to reduce delay and power dissipation is reduced with the use of high threshold voltage devices. The design has been implemented in a 90-nm BSIM4 level-54 CMOS technology. Simulation is carried in tanner v15.0 software at schematic level. Simulation results show that the design converts minimum of 0.1 V input signal into 1 V output signal. The level shifter has propagation delay of 10.99 ns and power dissipation of 1.52nW. The operating condition for the proposed design: VDDL = 0.2 V, VDDH = 1 V.

This paper presents an energy efficient voltage CMOS voltage level shifter. Voltage level shifter is used for multi-supply design applications. The main purpose of voltage level shifter is to convert the voltage level from one level to another. We verified our voltage level shifter in ASAP7 7nm Fin-Fet technology. The proposed voltage level shifter is based on differential cascade voltage switch logic, which takes an input voltage in the range of 0.25V to 0.6V and provides an output of 0.7V. Our voltage level shifter improves propagation delay and power dissipation with 48% and 43%, respectively, with recently reported Wilson current mirror voltage level shifter with Zero-Vth design. The proposed design technique comes up with significantly lower power consumption and drastically reduced propagation delay over a wide range of temperatures (-25 to 25 degree Celsius), as compared to existing technologies.

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability.

A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 μm CMOS technology occupies a silicon area of only 25 μm×25 μm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDL</sub> =0.8 V, and a capacitive load of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> =0.1 pF.

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.

In this concise, ultra low power and high speed voltage or logic LS circuit is introduced. With the help of regulated cross coupled structure in the pull up region the power utilized by the circuit is considerably decreased and speed of the circuit is also increased. The LS can convert the input logic levels or voltages below the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> of the transistor to the higher acceptable levels. A LS requires less area because it consists of less number of components which makes it fit for low power and high speed applications, for example implantable clinical gadgets and remote sensor organizations. Tool used for simulation is LTspice 180nm technology. The LS can shift the input voltage or logic levels as less as 80mv to higher acceptable levels. The power utilized by LS is 149.5nw and propagation delay is 23.7ns.

Modern electronic systems increasingly operate across multiple voltage domains, necessitating robust and efficient level shifter (LS) circuits to ensure reliable inter-domain communication. In low-power digital applications, minimizing propagation delay and transition time is critical for achieving high-speed and energy-efficient operation. This work presents a high-performance level shifter optimized for integration within Li-ion battery charger systems. The proposed design achieves a substantial reduction in propagation delays from 0.15 to 0.09062 ns while preserving signal integrity. When integrated with a gate driver, the overall structure exhibits a propagation delay of 0.20468 ns and a transition time of 0.014 ns, marking a significant improvement from the previous 0.036 ns. Furthermore, the proposed circuit occupies only 0.00039 mm² of silicon area, representing a 92% reduction compared to prior implementations (0.05 mm²). The complete design was implemented using Taiwan semiconductor manufacturing company (TSMC) 130 nm complementary metal–oxide– semiconductor (CMOS) technology, with both schematic simulation and layout carried out in the Cadence Virtuoso design environment. These results underscore the potential of the proposed solution for compact and high-efficiency system-on-chip (SoC) battery management applications.

High speed and high voltage level shifter using cross-coupled circuits in GaN FET driver, has potential capability to achieve exceeding 200V/ns slew immunities and sub-ns propagation delay. However, it can be found that output of the level shifter is incorrect when the input signal pulse width is smaller than the trigger pulse width. It means that although it has smaller propagation delay, the level shifter cannot work correctly in wild range of input signal duty cycle. This paper presents a novel approach to achieve wilder range of duty cycle. Based on 0.8μm 600V BCD process, simulation results of the proposed circuit show that minimum width of signal pulse is less than 1ns with the floating ground from zero to 600V. The duty-cycle range can be extended from 60% to 96% when signal frequency is 20MHz and triggered pulse width is 10ns. At the same time, the level shifter’s propagation delay is 5.9ns, power rail slew immunities over 200V/ns and power consumption of the proposed level shifter almost equals to that of traditional circuit.

We report successful implementation of high-density 3D integration technology in the fabrication of advanced mixed-signal processors for infrared focal plane arrays. Separate analog and digital integrated circuits (ICs) were custom designed and fabricated in standard bulk CMOS technology in two different commercial foundries. The 3D interconnects were arrayed in a 256×256 format with a 30 micron pitch and had the form of through-silicon vias 4 micron in diameter and 30 micron deep. Completed 3D readout IC stacks were tested pixel by pixel, demonstrating operability of 99.9%. The 3D IC stacks were hybridized with infrared photodiode arrays and produced functional FPA imagers with 99.9% array operability and unprecedented performance. Such imaging arrays and other smart sensors enabled by 3D integration of sensing elements with sophisticated signal processing are of increasing interest for Internet-of-Things applications, from net-enabled surveillance to mobile health.

Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert a Level Shifter (LS) circuit. As a penalty consequence, traditional LS circuits insert a delay and extra power consumption in the design. The dynamical behavior of MDSV designs has brought a new condition, where LS inserted in the circuit can be in an idle state temporally. This work presents a new architecture to reduce the power consumption and delay, bypassing the LS. The architecture explores an alternative path to current flow in the cases that LS is idle. With this new approach we reduce up to 15% of power consumption and up to 75% and 15% of delay.

In this work, we have presented the design of voltage level shifter using carbon nanotube field effect transistors (CNTFETs). The proposed design is capable of converting two input voltage levels to two output voltage levels. The threshold voltage of CNTFETs is suitably chosen to achieve the desired output. The proposed design can perform both up and down shifting which is very useful in the system-on-a-chip design to interface with other peripherals. It exhibits lower delay and power delay product in comparison with the existing complementary metal–oxide–semiconductor-based voltage level shifters. The proposed circuit is very effective as it eliminates the requirement of additional voltage level shifter for designing systems with multi-power supply voltage domain in the nanoscale regime. The design has been analyzed for different process, voltage and temperature corners. It has been shown that the design works perfectly with [Formula: see text] variation in the diameter of the carbon nanotubes used in the CNTFET. The performance varies slightly with [Formula: see text] variation in operating voltage. Our analysis shows that the design is thermally stable for a wide variation in operating temperature.

In high-frequency gate drivers, especially for wide-bandgap applications, hundreds of voltages per nanosecond noise would be generated. Therefore, the sub-ns delay level shifter with high dV/dt immunity is necessary for signal conversion among different voltage domain areas. This article presents design techniques for the sub-ns delay level shifter with ultrahigh dV/dt immunity. The propagation delay of the proposed floating level shifter is dramatically reduced by utilizing the edge detection technique. In order to further improve the performance, auxiliary pull-up circuit, promoting delay matching, and self-calibration techniques are adopted, which make the proposed level shifters more suitable for high-frequency wide-bandgap applications. The level shifter is fabricated in a 0.5 μm bipolar CMOS DMOS (BCD) process, whose results demonstrate the final level shifter achieves zero static power consumption, a 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, and dV/dt immunity up to 250 V/ns. The measurement results show that the sub-ns delay level shifter can be realized, and the minimum delay is only 664 ps at VSSH 25 V. Its figure of merit is just 0.044 ns/(μm × V), which is optimal among previous level shifters. The level shifters are also simulated at the 0.18 μm BCD process, and the propagation delay can be decreased by more than 60%.

Synchronous Switching Power Converters (SSPCs), which are suitable for fast-response high-efficiency applications, have become one of the research hot spots in recent years. A novel high-speed level shifter circuit with low power consumption is proposed in this paper, which is embedded in an integrated synchronous rectifier gate driver system. The proposed level shifter circuit consists of two parts: fast response circuit and low power hold circuit. Based on standard 0.35μm BCD process, the proposed level shifter circuit is validated. The results show that the level shifter circuit can realize 40ns response with a maximum current consumption of 6μA.

We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130 nm CMOS technology. At 1.2 V and 25 C, the 32-bit adder has a critical path delay of 921 ps and average power dissipation normalized to 600 MHz operation of 0.786 mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149 ps in 130 nm technology at 1.2 V and 25 C and 560 ps in 90nm technology at 1.0 V and 25 C. The 40-bit adder's average power dissipation normalized to 600 MHz operation is 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.

Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.KeywordsNumber systemArithmetic and Logic circuitsChip areaMultiple-Valued Logic (MVL)Quaternary logicTernary logicTiming delayVLSI