High performance communication using a commodity network for cluster systems

Path round-trip delay, i.e., path round-trip time (RTT), is one of the key metrics for evaluating network performance, also plays a crucial role in several overlay network construction protocols, peer-to-peer (P2P) applications, etc. In this paper, we present HPAP, a high precision active probe for path RTT measurement, which is based on Berkeley Packet Filter (BPF) technology. When the measuring probe packets arrive at or depart from the Network Interface Card (NIC), the BPF can capture them quickly, and can mark the timestamps immediately. The HPAP can calculate the path RTT value according to these timestamps. By this method, the time-stamp position can be removed from application program to data link layer of TCP/IP stack. The experimental results show that the new scheme can nearly eliminate the location error, and can practically improve the path RTT measuring accuracy. This scheme has low-cost in the investment, so it can be applied widely.

Zero-copy means on any network node, during message transmission, there is no data copy among memory segments and all messages transmission are operated directly between user application space and outside of network through network interfaces. By DMA technology, network interface devices can store data packets into the address where it can be accessed directly by user application, the data packets copy operation is removed in kernel and reducing the data transmission path. By working together with TOE technology, it can drop the communication delay effectively and save a lot of CPU cost. In this paper, we based on Linux (kernel version 2.6.11), by modifying its network device driver snull.c (attached in Linux Device Driver version 3), to implement the memory mapping between Linux kernel space to user application space. The main method we used is the combination of MMAP and PROC procedures, and at the end, we also introduce the implementation of test program and the test strategies. The test results show us that the applications can access the applied memory of kernel by mapping

MPI/MBCF is a high-performance MPI library targeting a cluster of workstations connected by a commodity network. It is implemented with the Memory-Based Communication Facilities (MBCF), which provides software mechanisms for users to access remote task's memory space with off-the-shelf network hardware. MPI/MBCF uses Memory-Based FIFO for message buffering and Remote Write for communication without buffering from among the functions of MBCF. In this paper, we evaluate the performance of MPI/MBCF on a cluster of workstations with the NAS Parallel Benchmarks. We verify whether a message passing library implemented on the shared memory model achieves higher performance than that on the message passing model.

The practical validation of investigating new router architectures and control algorithms is troublesome. It is partially due to the lack of programmable architectures that are fast enough for current networking, widely programmable, and equipped with the great variety of protocols that routers and switches has to handle. The idea of open, software-based routers running on commodity hardware have spread in recent years, resulting several practical implementations of so called soft-routers. Beside the economic advantages of having the Forwarding Element functions tackled by commodity Network Interface Cards (NICs), this approach suffers from issues of sub-optimal performance. This is partly due to the fact that all forwarding decisions are made by the main CPU instead of involving local processors at the NICs. Separating the functions into Forwarding Element and Control Element by the ForCES framework enabled the development of new control algorithms and protocol implementations for routers, however there are no widely available implementations. This paper describes a solution that is utilizing programmable hardware accelerators at the Forwarding Element, while keeping the advantages of open, Linux-based software-based router implementations. The hardware accelerators are implemented in the C-board, a reconfigurable, FPGA-based networking platform. The interoperability with existing Control Elements are described together with an analysis of features and capabilities of this combined solution.

The Network Driver Interface Specification (NDIS) is the specification for network driver architecture that allows transport protocols such as TCP/IP, Native ATM, IPX, and NetBEUI to communicate with an underlying network adapter. The implementation of this specification is an applicative framework for developing network device drivers. Network device drivers provide access for Windows Embedded Compact 7 based devices to local and wide area networks. The Windows Embedded Compact-based communications architecture supports network device drivers' implemented using Network Driver Interface Specification (NDIS) framework as well as technologies such as Remote NDIS (RNDIS), NDISWAN, Token Ring, Wi-Fi, IrDA, and Bluetooth.KeywordsShared MemoryNetwork AdapterDevice DriverNetwork Interface CardFunction ImplementationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

peer reviewed

Parallel processing in the era of many-core processors demands high-performance networks-on-chip and parallel communication based on intra-chip message passing. In this context, wireless networks-on-chip (WiNoCs) emerge to improve inter-core communication, bringing high bandwidth and low power consumption. In order to increase application performance, WiNoCs can support single-hop or multi-hop communication. The main issue is related to the performance of each communication architecture in the face of different parallel workloads. For this reason, the goal of this work is to evaluate and compare single- and multi-hop WiNoC architectures using parallel applications. The methodology is based on simulations done using the well-known simulator Network Simulator 2 (NS-2) and applications from NAS Parallel Benchmarks (NPB). The WiNoC architectures are based on 2-D mesh topology and ultra wide band (UWB) radio technology. The inter-core transmission is evaluated concerning unicast communication (1:1 and N:1) and broadcast communication (1:N and N:N). This work has, as contribution to the state-of-the-art, the evaluation of both WiNoC designs (single- and multi-hop architectures) with parallel applications. Based on our results, the single-hop architecture has lower communication delay than the multi-hop version, and for some workloads, there were no packet losses. However, to achieve high-performance communication, the single-hop architecture consumed 63.12 J for the 256-node network, versus 0.22 J consumed by the multi-hop version. Although single-hop WiNoCs reduce network bottlenecks and increase communication parallelism, they are recommended when energy consumption is not a critical factor.

The IEEE 802.11ac supports gigabit speeds by extending 802.11n air-interface features and increases the number of rate options by more than two times. Enabling so many rate options can be a challenge to rate adaptation (RA) solutions. Particularly, they need to adapt rates to various fast-changing channels; they would suffer without scalability. In this work, we identify three limitations of current 802.11ac RAs on commodity network interface cards (NICs): no joint rate and bandwidth adaptation, lack of scalability, and no online learning capability. To address the limitations, we apply deep reinforcement learning (DRL) into designing a scalable, intelligent RA, designated as experience driven rate adaptation (EDRA). DRL enables the online learning capability of EDRA, which not only automatically identifies useful correlations between important factors and performance for the rate search, but also derives low-overhead avenues to approach highest-goodput (HG) rates by learning from experience. It can make EDRA scalable to timely locate HG rates among many rate options over time. We implement and evaluate EDRA using the Intel Wi-Fi driver and Google TensorFlow on Intel 802.11ac NICs. The evaluation result shows that EDRA can outperform the Intel and Linux default RAs by up to 821.4% and 242.8%, respectively, in various cases.

This work focuses on the use of functional qualification for measuring the quality of co-verification environments for hardware/software (HW/SW) platform models. Modeling and verifying complex embedded platforms requires co-simulating one or more CPUs running embedded applications on top of an operating system, and connected to some hardware devices. The paper describes first a HW/SW co-simulation framework which supports all mechanisms used by software, in particular by device drivers, to access hardware devices so that the target CPU’s machine code can be simulated. In particular, synchronization between hardware and software is performed by the co-simulation framework and, therefore, no adaptation is required in device drivers and hardware models to handle synchronization messages. Then, CertitudeTM, a flexible functional qualification tool, is introduced. Functional qualification is based on the theory of mutation analysis, but it is extended by considering a mutation to be killed only if a testcase fails. Certitude(TM) automatically inserts mutants into the HW/SW models and determines if the verification environment can detect these mutations. A known mutant that cannot be detected points to a verification weakness. If a mutant cannot be detected, there is evidence that actual design errors would also not be detected by the co-verification environment. This is an iterative process and functional qualification solution provides the verifier with information to improve the co-verification environment quality. The proposed approach has been successfully applied on an industrial platform as shown in the experimental result section.

In order to develop a high-performance computing system, not only a high-performance processor and accelerator, but also the system software for optimizing system performance and providing an efficient programming environment is essential. We are developing a device driver for a new parallel computing accelerator (called XPU). The driver aims to support OpenCL and control the XPU. As a first step, we developed XPU driver emulator (XDE) based on the XPU simulator to validate the design of the XPU hardware and device driver prior to hardware manufacturing. XDE supports OpenCL and offloads parallel computations to XPU simulator. XDE allows early development of runtime and compiler. This paper presents the architecture, functions, and operational flow of the XDE. This provides an opportunity to understand the XPU device driver to be developed in the future and technical considerations for the co-designing of hardware and system software.

This paper describes the implementation of video encryption network card based on FPGA to ensure data secure in the process of Internet transmission. The overall design of the system is introduced. FPGA is used to implement data encryption and control function. Ethernet MAC controller is applied to send or receive data over the network. For software design, it mainly focuses on the network device driver in this paper. At the requirement of large image data and real-time image processing, this design also presents two ways to improve the efficiency of data transfer. On the one hand, an image encryption algorithm based on ZUC stream cipher is adopted, with fewer FPGA resources and faster encryption. On the other hand, a DMA engine is applied to manage data transmission between host memory and FPGA to accomplish high performance data transfer.

This paper evaluates the performance of three popular technologies used to interconnect machines on clusters: Fast Ethernet, Myrinet and Giganet. To achieve this purpose, we used the NAS Parallel Benchmarks. Surprisingly, for the LU application, the performance of Fast Ethernet was better than Myrinet. We also evaluate the performance gains provided by VIA, a user lever communication protocol, when compared with TCP/IP, a traditional, stacked-based communication protocol. The impacts caused by the use of Remote DMA Write are also evaluated. The results show that Fast Ethernet, when combined with a high performance communication protocol, such as VIA, has a good cost-benefit ratio, and can be a good choice to connect machines on a small cluster environment where bandwidth is not crucial for applications.

This paper presents the design and implementation of ART-Linux - a low-latency real-time extension of the Linux kernel for high-frequency system control. It is particularly tailored for the Intel x86 architecture, providing real-time (periodic) task execution system calls in user-space. ART-Linux provides simple yet strong system calls to allow periodic real-time programs to run in user-space with existing Linux device drivers, while providing users with standard developing, executing, debugging, and investigating environments. There is no need to add special device drivers. In order to achieve real-time functions in the Linux kernel, ART-Linux introduces the following techniques: 1) a mutualexclusive execution mechanism realized by virtual processor numbers, 2) a transfer queue to avoid mutex-locked mutual-exclusive execution, and 3) a multi-level priority inversion function. A finegrained implementation tuning of these techniques achieves very small jitters for specified periods (less than 20[μs] in practice). Experimental results using a well-known humanoid robot called HRP-2 no.12 demonstrate that jitters of cycle times are retained in an acceptable range for humanoid control.

Clusters of PCs are increasingly popular as cost-effective platforms for supercomputer-class applications. Given recent performance improvements in graphics accelerators, clusters are similarly attractive for demanding graphics applications. We describe the design and implementation of Lightning-2, a display subsystem for such a cluster. The system scales in both the number of rendering nodes and the number of displays supported, and allows any pixel data generated from any node to be dynamically mapped to any location on any display. A number of image-compositing functions are supported, including color-keying and depth-compositing. A distinguishing feature of the system is its platform independence: it connects to graphics accelerators via an industry-standard digital video port and requires no modifications to accelerator hardware or device drivers. As a result, rendering clusters that utilize Lightning-2 can be upgraded across multiple generations of graphics accelerators with little effort. We demonstrate a renderer that achieves 106 Mtri/s on an 8-node cluster using Lightning-2 to perform sort-last depth compositing.

The reliability of hardware devices is of critical importance to the overall stability of operating systems. Drivers assume that hardware devices always work normally, but this assumption may cause drivers or systems to crash, since hardware device failures occur frequently. This can lead to incorrect values for drivers and cause them to malfunction. This paper proposes an advanced graph model for tainted variable tracking. The proposed approach can efficiently find variables, which are related to values read from hardware devices. It can also be used for variable assignment tracking, which is of great benefit in improving the reliability of hardware devices and drivers.