High Performance Direction Finding Algorithm Based on Phase Locked Loop

The Software-Defined Radio (SDR) receiver [1-5] has been developed at the Telecommunications Laboratory (TL, Chinese Taipei) for implementation in two-way satellite time and frequency transfer (TWSTFT/TW) Earth stations, aiming at improving the stability of TW time transfer, with particular impact on the diurnal signature present in almost all the links, which is the major uncertainty source in TW time links. The BIPM and the Consultative Committee for Time and Frequency (CCTF) Working Group on TWSTFT launched in February 2016 a pilot study for validating the SDR receiver in view of its implementation for use in UTC time links. Participants to this pilot study are the laboratories contributing to UTC which operate the SDR receiver and the BIPM Time Department. Goals of the pilot study are first, to validate the efficacy of the SDR receiver for improving the TWSTFT uncertainty and significantly reduce the diurnal effects; second to implement routine TW code measurement data through SDR receiver to improve the UTC time comparisons. In the frame of the pilot study, the SDR receiver has been installed and is operational by the end of 2016 at TL, NICT, KRIS, NTSC in Asia, PTB, OP and SU in Europe and NIST in the US. The project to install the SDR receiver in all the TW laboratories is ongoing. We present the results obtained at the BIPM Time Department in the preliminary steps of the analysis and validation of the SDR measurement data by using different methods, such as the time deviation (TDev), the triangle closures, the comparison with GPSPPP [6]. We analysed the data obtained from the pilot study and observed that in some TW links there is significant improvement, while in others no noise reduction is visible. This preliminary result needs more investigation, together with other open points as the calibration, the discontinuities observed after restarting the receiver etc. If the conclusion of this pilot project is positive, a proposal could be discussed at the CCTF to include TW time links with the SDR receiver in the computation of UTC. We study also the potential strategies to further improve the TWSTFT SDR; its combination with GNSS links [7] and the computation of SDR indirect links [8, 9].

A digital signal processing (DSP)-type phase synchronizer based on the method of least squares (PS-MLS) is proposed that can replace the conventional circuits for phase synchronizers, such as phase-locked loops (PLLs). The construction of PS-MLS is different from that of PLLs. The proposed PS-MLS has advantageous characteristics compared with the conventional DSP-type PLLs and can satisfy three important points of PLLs simultaneously: fast acquisition, wide pull-in range, and good noise suppression. Only two steps are required for the acquisition (in a noise-less case), the condition to accomplish synchronization is relaxed, and is equal to the sampling theorem (fi>or=2fs), and the noise suppression performance is greatly improved compared with the conventional PLL. >

Direction finding techniques can be applied to a number of military and civilian systems, such as radar, sonar, and radio communications. It aims at finding the Direction of Arrival of an electromagnetic source for positioning purposes. Direction finding systems can be primarily classified as multiple or single channel. The single-channel solution, investigated herein, is based on a switched antenna associated to a special Phase Locked Loop (PLL) receiver architecture that allows tracking the phase of each antenna. The PLL output is processed by a signal processing block that removes the ambiguity inherent to the PLL and estimates the angle of arrival of the source. This procedure is usually linked to high computational complexity that increases with the number of antennas and with the modulation level. This article proposes a technique to decrease the computational burden of the PLL-based single receiver DOA estimation scheme and to use the super resolution algorithm Multiple Emitter Location and Signal Parameter Estimation to obtain azimuth and zenith angles with improved accuracy. The simulated results using the novel algorithm are shown and its performance compared to the traditional solution in different scenarios.

Ionospheric scintillation occurs for transionospheric radio waves propagating through random ionospheric irregularities, which affect the phase and/or amplitude observations made by the receiver. Generally, the scintillation induces excess carrier phase jitter in the phase lock loop (PLL) of the GPS receiver, and strong scintillation can cause a conventional PLL (ATAN [arctangent method], constant bandwidth Bn = 10 Hz) to lose phase lock resulting in no GNSS signal available at that time from the satellite path(s) affected. A PLL with a larger bandwidth is one solution to mitigate this but at the expense of extra phase noise, and this may not be an optimal solution during weak scintillation conditions. This study uses a novel WBMod (Wide Band Modeling) assisted PLL for robustness of availability of GPS services with lower introduction of extra phase noise. At the initial stage, an optimal PLL bandwidth is predicted using WBMod to stabilize the PLL during strong phase scintillation. A FAB (Fast Adaptive Bandwidth) PLL is used to minimize the phase error. To investigate this approach, a realistic scintillated signal is produced using 50 Hz raw GPS signal observations (carrier phase and intensity) collected at Yellowknife (Yell, 64.48° N, -114.52° E) in a Matlab-based GPS software receiver.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

International audience

The conventional PLL (phase locked loop) frequency synthesizer has a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are a serious problem because the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit which makes the negligible overshoot and much shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. Also, the hardware complexity and power consumption are decreased to about 28%, as compared with the conventional DH-PLL. The high speed switching characteristic in the frequency synthesis process is verified by computer simulation.

In practical applications such as radar, sonar, and mobile communications, transmitted signals are often affected by the scattering and reflection phenomena, which causes the signal energy received by the antenna array to be distributed into a certain space. In this case, a distributed source model will be more applicable. In general, the distributed sources have been classified as coherently distributed (CD) source and incoherently distributed (ID) source, which prove to be suitable for the cases of slowly time-varying and rapidly time-varying channels, respectively.In this paper, we consider the two-dimensional direction of arrival (DOA) estimation of distributed sources (including CD source or ID source). Specifically, uniform circular array (UCA) is widely used because of its ability to measure full azimuth angle and high resolution. However, the existing estimation algorithms all require spectral peak searching and the eigenvalue decomposition, which can bring a large computational complexity. To solve this problem, a decoupled rapid two-dimensional DOA estimation algorithm is proposed based on vectoring differential phases considering the two cases of single CD source and ID source. Firstly, based on spatial frequency approximation model, it is proved that none of differential phases between the received signals of different sensors in the UCA is affected by angle spread parameters when there is only a single distributed source. Under the premise of such a property, the central DOAs can be decoupled through obtaining the differential phases. Next, we can obtain the phase angles of strictly upper triangular elements in the sample covariance matrix, which correspond to differential phases between different sensors. Finally, by vectoring these differential phases, the central azimuth and elevation DOAs are estimated in the closed form from a least-squared problem, where the spectral peak searching and eigenvalue decomposition can be avoided, hence the computational complexity is reduced greatly. Theoretical analysis and simulation results show that the proposed algorithm has higher estimation accuracy and does not require prior information about the distribution of angular signals. With both low computational complexity and low hardware complexity, the proposed algorithm is beneficial to the engineering practice of array direction finding in complex environment.

In this paper, a triple-controlled direct digital synthesis (DDS)-based phase-locked loop (PLL) for 3 to 4 GHz frequency synthesis is presented. The architecture has the merits of low spurs, a fast switching speed and high frequency resolution. It corrects the output of DDS and changes the division ratios of two variable frequency dividers in PLL to avoid high level spurs falling in the loop bandwidth of PLL. The additional DAC output is added to the output of the loop filter to drive the VCO. It provides the PLL with a fast switching speed. Experiment and measurement results showed that this type of frequency synthesizer architecture has better performance than conventional PLL and can be used in most applications of frequency synthesis.

The International Bureau of Weights and Measures and the Consultative Committee for Time and Frequency Working Group on Two-Way Satellite Time and Frequency Transfer (TWSTFT) have stimulated a pilot study on using software defined radio (SDR) receivers for TWSTFT in the framework of the realization of Coordinated Universal Time. The SDR receivers based on a software developed by TL have been set up at PTB, OP and NIST during the summer and fall of 2016. Continuous SDR TWSTFT measurements have been established for the OP/PTB, NIST/OP and NIST/PTB links. From the SDR TWSTFT clock comparison results (TWSTFT difference), we observed that the commonly present but undesired diurnal pattern in the OP/PTB SDR TWSTFT difference is greatly reduced compared to the diurnal pattern in the difference obtained from the regular (nonSDR) TWSTFT equipment. However, the diurnal reduction in the NIST/OP and NIST/PTB SDR TWSTFT differences is not as significant as in the OP/PTB link. This is a strong indication that the application of SDR receivers has the ability to significantly improve the stability of some TWSTFT links, but is not a solution for all links. In this paper, we will analyze the diurnal reduction using the SDR receivers for the three links and study the dominant causes for the diurnal effect in the EuropeEurope and transatlantic TWSTFT links.

Background: The phase-locked loop (PLL) is widely used to estimate synchronization information such as magnitude and phase angle of the grid voltage, which is essential for gridconnected power generation from distributed renewable energy sources. However, the harmonics in the grid often affect the accurate extraction of fundamental positive sequence, resulting in phase deviations. Methods: A dual extended novel third-order generalized integrator (DENTOGI) is proposed and placed into the control outer loop of the PLL. This approach can be applied in the condition of the grid with DC offset voltage (DCOV). Additionally, the PLL is proposed by introducing moving average filter (MAF) and eliminating the proportional controller of the integration link to suppress high-frequency harmonics and speed up the response. Results: A comparative experiment using Matlab/Simulink is conducted to evaluate the proposed PLL against the conventional PLLs. The experimental results confirm that the proposed PLL exhibits superior filtering performance for DC offset and harmonic components when compared to the conventional PLL. Additionally, the proposed PLL demonstrates better dynamic adjustment capabilities. Conclusion: The main contribution of this paper is to propose a phase-locked method that can eliminate DCOV and harmonic components, which can be applied in non-ideal power grid conditions. The proposed PLL based on DENTOGI and MAF can lock the grid phase stably without errors under the grid fault involving DCOV and harmonic disturbance, it also exhibits the characteristics of fast response.

The object of this study is the process of determining the coordinates of an air object. The main hypothesis of the study assumed that the use of a network of two Software-Defined Radio (SDR) receivers would make it possible to determine the coordinates of an air object. The determined coordinates could be used as preliminary target designation for the radar. A method for determining the coordinates of an air object by a network of two SDR receivers has been improved, which, unlike the known ones, involves: – using signals from the airborne systems of the air object; – using SDR receivers as network elements; – using the triangulation method for determining the coordinates of an air object. The accuracy of determining the coordinates of an air object by a network of two SDR receivers has been assessed. It was found that: – the accuracy of measuring the coordinates of an air object decreases sharply as the polar angle of observation from the middle of the base approaches 0 or π; – the smallest coordinate measurement error can be ensured when the air object is located on the traverse to the middle of the base and when the distance to the air object is close to the base size; – with small bases, the non-uniformity of the dependence of the coordinate determination error on the position of the air object relative to the SDR receivers is more pronounced than with large ones; – at a long range, the error values for small bases grow rapidly, which is primarily due to the small angle of intersection of the bearing lines; – it is advisable to place SDR receivers at a sufficiently large distance from each other (recommended value: (1–3) times the distance to the air object); – the errors of measuring the coordinates of the air object have a value of (250–350) m in a sufficiently wide range of directions; – with a decrease in the base size, the errors grow rapidly (reaching a value of more than 1000 m) when the observation angle deviates from the 90° direction

The most computationally intensive part of a software defined radio (SDR) receiver is the channelizer, which extracts multiple narrowband channels from a wideband input signal. In an SDR receiver, the compatibility of the channnelizer with different wireless communication standards is guaranteed by its reconfigurability. In this paper, we present the implementation of a reconfigurable channelizer based on tree-structured quadrature mirror filter (QMF) banks using Texas Instruments TMS320C6711 digital signal processor (DSP). Experimental results show that the proposed channelizer offers better adjacent channel interference attenuation and low complexity when compared with conventional Discrete Fourier Transform (DFT) based channelizer.

A novel design for a phase-locked loop (PLL) frequency synthesizer is proposed to obtain a fast acquisition time. For conventional PLL frequency synthesizer design, the smallest frequency increment is the same as the reference frequency. Thus, a low reference frequency can only be used at the expense of a longer acquisition time. However, in the proposed PLL synthesizer, by introducing n-stage novel type cycle swallowers, the smallest frequency increment and the reference frequency can be made to be independent of each other. Therefore, by using higher feedback and reference frequencies, the proposed synthesizer can attain an acquisition performance over 10/sup 3/ times faster than that of the conventional PLL synthesizer and maintain the same smallest frequency increment for the output frequency. The performance of the design is illustrated by experimental results. >

Conventional back-EMF based sensorless control methods suffer the harmonic fluctuation of position estimation owing to the 5th and 7th current harmonics brought by the inverter nonlinearities. In this paper, a linear extended state observer (LESO)-based position estimation method with an improved phase-locked loop (PLL) is proposed to eliminate the harmonic fluctuation. Two LESOs provide the chattering-free estimation of back-electromotive force (EMF) for both α-and β-axis. A second-order generalized integrator (SOGI) is incorporated into the conventional PLL, thus eliminating the 6th harmonic component of the position estimation error in the feedforward path of the PLL. Compared with the state-of-art proposals, which normally utilize at least four SOGIs or other kinds adaptive filters to eliminate the 5th and 7th harmonics of the estimated back-EMF for both α- and β-axis, the proposed method only employs one SOGI while still holds a good position error harmonics elimination performance. In this way, the system complexity and computational burden can be significantly reduced. Simulation results confirm the effectiveness of the proposed method.