High-performance divider using redundant binary representation

This paper proposes a square root hardware algorithm using the redundant binary representation in the internal computation. A discussion is made for the realization of a combinational square‐rooter based on the algorithm. This paper considers the computation of the mantissa in square‐rooting for the binary normalized floating‐point representation. The proposed algorithm is a kind of subtract‐and‐shift square‐root method. Partial remainders are represented by the redundant binary representation, where each digit is an element of {‐1, 0, 1}. Then each digit of the square root is determined from {‐1, 0, 1}, by examining the upper three digits of the partial remainder. The computation for the partial remainder is affected in the redundant binary number system. Finally, the square root determined in the redundant binary representation is converted into the ordinary binary representation. In the redundant binary representation, the addition of two numbers can be effected without carry propagation. Consequently, by using the combinational circuit, each digit of the square root can be determined in a constant time, independently of the number of digits of the operand. The computation time for the n‐bit square rooter (number of stages) is proportional to n. The number of logic elements in the circuit is proportional to n2. The hardware structure is a regular cellular array, which is suited for VLSI implementation. When the circuit is implemented on a VLSI chip, the chip is proportional to n2. The proposed square rooter has nearly the same circuit structure and the hardware complexity, compared with the conventional subtract‐and‐shift square rooter using ripple carry adder. The computation time is approximately one‐fifth for 32‐bit and one‐tenth for 64‐bit, compared with earlier circuits.

Redundant binary (RB) representation possesses some figures of merit as an internal format for the design of datapath components due to its carry-free property and avoidance of sign extension. Being a non-classical representation, its worth in meeting conflicting VLSI goals has not been fully evaluated. This chapter presents a structural and systematic approach to the design and analysis of different Booth multipliers in RB representation by decomposing them into several key building blocks. The design considerations on each of these generic constituent modules and their logic circuits are first discussed qualitatively and independently before they are selectively fused into different configurations of Booth multipliers. To unify the heterogeneous fabrics designed with different coding formats together, simple anterior and posterior converters are derived for their interfacing. Altogether 21 different RB multiplier architectures have been constructed with various configurations of partial product encoding, generation and reduction to analyze their design trade-offs in terms of area, delay, and energy consumption. These multipliers have been implemented and compared for various VLSI metrics with six commonly used operand lengths varying from 8 bits to 64 bits. The intriguing augmentation and restriction between different architectural modules inferred from this comparative study are inspirational to innovative RB multiplier design. It is shown that a large design space can be explored from sensible topological combinations of different constituent modules of RB multiplier architecture for the desirable performance characteristics.

In the paper we make a comparative study of two techniques to design error-detectable array architectures. These techniques are the redundant binary representation (RBR) where the data is encoded in the 1-out-of-3 code; and the two-rail logic where the data is encoded in the 1-out-of-2 code. In recent work, the RBR has been used to achieve online error detection and localisation by checking the data on the array borders. Here we show that another approach is also possible, with less hardware cost, where the checking takes place on the local (processor) level. This provides immediate error detection without delay. The performance of the RBR approaches has been compared with the two-rail approach. The results show that the RBR approaches require more hardware overheads, for small word lengths (n). However, the hardware cost of the two techniques are approximately the same for large n, while the RBR approaches offer much faster arithmetics for all n.

Modern digital communication systems rely heavily on baseband signal processing for in-phase and quadrature (I-Q) channels, and complex number processing in low-voltage CMOS has become a necessity for channel equalization, timing recovery, modulation, and demodulation. In this work, redundant binary (RB) arithmetic is applied to complex number multiplication for the first time so that an N-bit parallel complex number multiplier can be reduced to two RE multiplications (i.e., an addition of N RB partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RB partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5 K transistors is integrated on 1.05/spl times/1.33 mm/sup 2/ using 0.8 /spl mu/m CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at 200 MHz.

A fast multiplier with a new Redundant Binary Booth's Encoding (RBBE) for Radix-8 has been developed. The new RBBE enables one to directly generate all Redundant Binary Partial Products (PP) including the hard multiple of 3/spl times/Multiplicand with no additional circuitry or time delay. Also, the use of TGs in Partial Product Selection Circuit permits the rapid generation of PPs. In this work, a word size of 54 bits is chosen to comply with the IEEE double-precision floating-point standard, which consists of one sign bit and 53 bits of fraction. Thus, the RBBE unit for Radix-8 generates 18 Redundant Binary PPs to be accumulated by a Redundant Binary Adder (RBA) tree. Due to the simplicity of the necessary interconnections between the adders, the RBA tree has a regular layout. The output of the RBA tree is in the Redundant Binary (RB) form, which needs to be converted to Standard Binary (SB) form. Although this conversion can be performed by a Carry Look Ahead (CLA) adder, a better conversion circuit has been designed to take advantage of the RB number system. The proposed design contains a converter of a higher speed and a lower transistor count. As a result, the proposed fast multiplier accepts two 54 bit SB numbers and produces a final product of 108 bit SB number.

A multiplier which can accept redundant binary number inputs is proposed using available unsigned multiplier (array multiplier, carry-save-addition tree multiplier, or multiplier using redundant binary representations). The proposed multiplier is applicable in redundant binary ALU unit or redundant binary processor.

We introduce a novel method for complex number representation. The proposed, redundant complex binary number system (RCBNS) is developed by combining a redundant binary number and a complex number in base (-1+j). Donald (1960) and Walter Penny (1964, 1965) represented complex numbers using base -j and (-1+j) in the classified algorithmic models. A redundant complex binary number system consists of both real and imaginary-radix number systems that form a redundant integer digit set. This system is formed by using complex radix of (-1+j) and a digit set of /spl alpha/=3, where /spl alpha/ assumes a value of -3, -2, -1, 0, 1, 2, 3. The arithmetic operations of complex numbers with this system treat the real and imaginary parts as one unit. The carry-free addition has the advantage of redundancy in number representation in the arithmetic operations. Results of the arithmetic operations are in the RCBNS form. The two methods for conversion from the RCBNS form to the standard binary number form have been presented. The RCBNS reduces the number of steps required to perform complex number arithmetic operations, thus enhancing the speed.

The Montgomery modular multiplication is an integral operation unit in the public key cryptographic algorithm system. Previous work achieved good performance at low input widths by combining Redundant Binary Representation (RBR) with Montgomery modular multiplication, but it is difficult to strike a good balance between area and time as input bit widths increase. To solve this problem, based on the redundant Montgomery modular multiplication, in this paper, we propose a flexible and pipeline hardware implementation of the Montgomery modular multiplication. Our proposed structure guarantees a single-cycle delay between two-stage pipeline units and reduces the length of the critical path by redistributing the data paths between the pipelines and preprocessing the input in the loop. By analyzing the structure and comparing the related work in this paper, our structure ensures a lower area-time product while achieving a controllable and small area consumption. The comprehensive results under different Taiwan Semiconductor Manufacturing Company (TSMC) processes demonstrate the advantages of our structure in terms of flexibility and area-time product.

An algebraic description of basic discrete symmetries (space reversal P, time reversal T, and their combination PT) is studied. Discrete subgroups of orthogonal groups of multidimensional spaces over the fields of real and complex numbers are considered in terms of fundamental automorphisms of Clifford algebras. In accordance with a division ring structure, a complete classification of automorphism groups is established for the Clifford algebras over the field of real numbers. The correspondence between eight double coverings (Dąbrowski groups) of the orthogonal group and eight types of the real Clifford algebras is defined with the use of isomorphisms between the automorphism groups and finite groups. Over the field of complex numbers there is a correspondence between two nonisomorphic double coverings of the complex orthogonal group and two types of complex Clifford algebras. It is shown that these correspondences associate with a well-known Atiyah–Bott–Shapiro periodicity. Generalized Brauer–Wall groups are introduced on the extended sets of the Clifford algebras. The structure of the inequality between the two Clifford–Lipschitz groups with mutually opposite signatures is elucidated. The physically important case of the two different double coverings of the Lorentz groups is considered in details.

The principle of redundant binary representation is used to design power and area efficient signed Vedic 8×8 multiplier architecture. The Urdhva Tiryakbhyam Sutra, which extends Vedic algorithms to signed numbers has been implemented in this work. The design is written in VHDL and synthesized on FPGA device using Xilinx ISE 14.4. In contrast to the traditional architectures considered, the proposed architecture performs better in terms of power.

A quantum theory representations of real (R) and complex (C) numbers is given that is based on states of single, finite strings of qukits for any base k > 1. Both unary representations and the possibility that qukits with k a prime number are elementary and the rest composite are discussed. Cauchy sequences of qukit string states are defined from the arithmetic properties. The representations of R and C, as equivalence classes of these sequences, differ from classical kit string state representations in two ways: the freedom of choice of basis states, and the fact that each quantum theory representation is part of a mathematical structure that is itself based on the real and complex numbers. These aspects enable the description of 3 dimensional frame fields labeled by different k values, different basis or gauge choices, and different iteration stages. The reference frames in the field are based on each R and C representation where each frame contains representations of all physical theories as mathematical structures based on the R and C representation. Approaches to integrating this with physics are described. It is observed that R and C values of physical quantities, matrix elements, etc. which are viewed in a frame as elementary and featureless, are seen in a parent frame as equivalence classes of Cauchy sequences of qukit string states.

For many years, vector space models have been used in information retrieval and computational linguistics to represent terms, queries, and documents, using vector addition as a simple operator to model semantic composition. Though surprisingly successful, many aspects of meaning including word order, typed relationships, and nested structures are not captured by this modelling process.

Humans make sense of mathematics by relating it to personal conceptions and experiences.This might not be a smooth process as it may involve conceptions that work in an old context but do not work in a new context.The framework proposed by Chin and Tall (2012), Chin (2013) and Chin (2014) highlights how prior experiences shape humans' conceptions can be either supportive or problematic in making sense of extended contexts of mathematics.A supportive conception is a conception that supports learning and generalisation in a new context while a problematic conception is a conception that impedes learning and generalisation in a new context.By employing this framework, this study aims to explore how a group of respondents that consists of 30 mathematics undergraduate students from a public university in Malaysia make sense of complex numbers.The system of complex numbers is an extension of real numbers thus students will learn real numbers prior to learning complex numbers.How the respondents cope with the transition from real numbers context to complex numbers context is the focus of this study.Data were collected through a questionnaire and follow up interviews.Respondents participated in the follow up interviews voluntarily and data from three respondents were reported in this study.The result shows that these respondents have several supportive conceptions, such as the concept of addition and multiplication of real variable.The data also support the existence of problematic conceptions in making sense of complex numbers, namely the concept of positive-negative numbers and inequalities.These conceptions are originated from the context of real numbers.

In this paper we discuss the important Abel's summation formula, which is a very powerful tool for analysing series of real or complex numbers. We derive from it an integral test which may be useful in cases where the classical integral test may not be applied. We also discuss how this new integral test may be used when one is dealing with alternating series of real or complex numbers. The main goal of this note is to provide a supplementary material for courses dealing with infinite series of real or complex numbers.

Although complex numbers are essential in mathematics, they are not needed to describe physical experiments, as those are expressed in terms of probabilities, hence real numbers. Physics, however, aims to explain, rather than describe, experiments through theories. Although most theories of physics are based on real numbers, quantum theory was the first to be formulated in terms of operators acting on complex Hilbert spaces1,2. This has puzzled countless physicists, including the fathers of the theory, for whom a real version of quantum theory, in terms of real operators, seemed much more natural3. In fact, previous studies have shown that such a ‘real quantum theory’ can reproduce the outcomes of any multipartite experiment, as long as the parts share arbitrary real quantum states4. Here we investigate whether complex numbers are actually needed in the quantum formalism. We show this to be case by proving that real and complex Hilbert-space formulations of quantum theory make different predictions in network scenarios comprising independent states and measurements. This allows us to devise a Bell-like experiment, the successful realization of which would disprove real quantum theory, in the same way as standard Bell experiments disproved local physics.