High secure buffer based physical unclonable functions (PUF’s) for device authentication

Physical Unclonable Functions (PUFs) are circuits which exploit the statistical variability of the fabrication process to create a unique device identity. PUFs have been used in the design of cryptographic primitives for applications like device authentication, key generation and intellectual property protection. Due to its small cost and design simplicity, delay-based Arbiter PUFs (APUFs) have been considered a cryptographic engine candidate for the integration into low-cost IoT devices (e.g. RFID tags). Although APUFs have been extensively studied in the literature, not much work has been done in understanding how to improve its response variability using VLSI design techniques. This paper uses extensive AMS 350nm SPICE-based Monte-Carlo simulation to analyze how the proper selection of arbiter element and gate sizing can affect the delay variability of APUFs. Experimental results show that the combination of the appropriate arbiter and gate sizing configuration can considerably improve the Hamming Weight distribution of the APUF response, thus resulting in more reliable and less biased designs.

Physical Unclonable Functions (PUFs) are promising security primitives for resource-constrained network nodes. The XOR Arbiter PUF (XOR PUF or XPUF) is an intensively studied PUF invented to improve the security of the Arbiter PUF, probably the most lightweight delay-based PUF. Recently, highly powerful machine learning attack methods were discovered and were able to easily break large-sized XPUFs, which were highly secure against earlier machine learning attack methods. Component-differentially-challenged XPUFs (CDC-XPUFs) are XPUFs with different component PUFs receiving different challenges. Studies showed they were much more secure against machine learning attacks than the conventional XPUFs, whose component PUFs receive the same challenge. But these studies were all based on earlier machine learning attack methods, and hence it is not clear if CDC-XPUFs can remain secure under the recently discovered powerful attack methods. In this paper, the two current most powerful two machine learning methods for attacking XPUFs are adapted by fine-tuning the parameters of the two methods for CDCXPUFs. Attack experiments using both simulated PUF data and silicon data generated from PUFs implemented on field-programmable gate array (FPGA) were carried out, and the experimental results showed that some previously secure CDC-XPUFs of certain circuit parameter values are no longer secure under the adapted new attack methods, while many more CDC-XPUFs of other circuit parameter values remain secure. Thus, our experimental attack study has re-defined the boundary between the secure region and the insecure region of the PUF circuit parameter space, providing PUF manufacturers and IoT security application developers with valuable information in choosing PUFs with secure parameter values.

Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

The quantitative performance indicators of Physical Unclonable Functions (PUFs)-Randomness, Steadiness, Correctness, Diffuseness and Uniqueness-are strictly defined and applied to the evaluation of 45 arbiter PUFs on Virtex-5 FPGAs. The indicators effectively reflect the characteristics of PUFs ranging from 0 to 1 with 1 being the highest performance. The indicators enable the easy measurement and intuitive understanding of PUF performances. The experimental results shows that the arbiter PUFs have excellent overall intra-device performances though a slight bit bias is indicated. The inter-device performance is moderate and will suffice for the practical use of PUFs for device authentication and so on. Additionally, the reliability of the obtained PUF performances is statistically discussed in terms of the Confidence Interval and the number of devices. This paper presents in detail the definitions of the performance indicators and the quantitative and statistical evaluation results of the arbiter PUFs.

Modern embedded electronic devices are gradually becoming an essential part of everyday lives, proving indispensable for daily activities. The growth of the Internet of things (IoT) technology fuels this phenomenon. IoT devices are found everywhere around us – smartphones, smartwatches, home automation, autonomous cars, and medical implants for human bodies. These devices find widespread use in medical imaging, video surveillance as embedded vision, cloud computing platforms, and military applications. Ensuring the reliability and safety of these devices is of prime importance, since these devices store sensitive data. A wide range of such embedded devices is a common target for intellectual property (IP) theft and reverse-engineering attacks by hackers to access confidential information and counterfeit integrated circuits. Physically unclonable functions (PUFs) are innovative hardware defense techniques that promise a fundamental change in our approach to many security problems. PUFs possess desirable properties like low cost, simple architectures, a light weight, versatility, and the valuable advantage of unclonability. This unclonable property is a consequence of intrinsic random variations at the micro- and nanoscale levels in the manufacturing processes and cannot be controlled or removed. This characteristic also serves as a unique fingerprint for the integrated circuit chips, similar to humans. The widespread usage of PUF techniques in security applications makes it imperative for hardware designers to appreciate its working and understand its uses in practice fully. This chapter aims to address these and other topics by presenting a detailed introduction of the concepts, evaluation parameters, and various ramifications of physically unclonable functions. PUF techniques also provide an economical alternative to ciphers and hash functions for secure cryptographic protocols. It is also necessary to provide security of IoT devices, have economic viability, and fit well with embedded devices’ heterogeneous nature. PUF circuits receive challenges as a sequence of bits and generate matching responses called a challenge-response pair, which can be thought of as a secret key or unique fingerprint. It also obviates the need for storing the keys in nonvolatile memories with dedicated protection, which is a costly affair. In this chapter, different PUFs, including optical PUF, delay-based PUFs, weak and strong PUFs, etc., the maturity of this technology, and their various applications are investigated. This chapter also emphasizes critical challenges toward PUF utilization in IoT and related fields and significant future development areas like critical public infrastructure, reconfigurability, and bit-specific reliability. The unique IoT domain protection criteria and how PUFs can be used to fulfill them are also examined. The chapter’s emphasis is on proven and well-understood strategies involving their benefits and shortcomings.

Physical Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from device manufacturing variations. Arbiter PUFs (APUFs) are a widely used class of PUF detecting process variations by exploiting the propagation delay differences between signals. However, both FPGA and ASIC implementations of APUFs suffer from systematic bias caused by either asymmetric routing or gradient effects in wafer doping. In this work, we introduce an improved APUF ASIC implementation achieving entropy enhancement without increasing area and power consumption significantly. In this design, a selector chain is divided into multiple blocks to avoid accumulation of systematic variation. Different voltage supplies are chosen for selector chain and arbiter circuit to overcome reliability problems produced by short chains. Cadence Monte Carlo sampling on 256-stage APUFs built in IBM 0.13µm technology shows the proposed Multi-Block (MB-) APUFs provide inter-chip uniqueness and reproducibility similar to double APUF (DAPUF); compared to DAPUF with similar uniqueness performance, MBAPUFs decrease area and power consumption by a factor of 2.

Physical unclonable functions (PUFs) are used to extract unique signatures from silicon-based chips which can be used for chip authentication and producing unclonable cryptographic keys. However, researchers have found that PUFs are vulnerable to various machine learning modeling attacks. In this work, we introduce a unique hybrid PUF structure that uses Challenge-Response Pairs (CRPs) from an Arbiter PUF and feeds them to an XOR-Inverter based Ring Oscillator to generate responses which makes the PUF less vulnerable to machine learning modeling attacks. From the results, it is found that the prediction accuracy when different machine learning classifier algorithms are employed to attack the PUF, is drastically reduced and lies in the range of 3.5% to 6.8%, whereas the ANN-based model accuracy obtained is in the range of 5.4% to 7.5%. Our study indicates that the new design’s vulnerability in terms of prediction accuracy against different machine learning modeling attacks is less by 51.6% for ML and 54.1% for ANN compared to other delay-based PUF designs.

A Physical Unclonable Function (PUF) is a physical system that leverages manufacturing process variations to generate unclonable and inherent instance-specific measurements of physical objects. PUF is equivalent to human biometrics in many ways where each human has a unique fingerprint. PUF can securely generate unique and unclonable signatures that allow PUF to bootstrap the implementation of various physical security issues. In this thesis, we discuss PUFs, extend it to a novel SW-PUF, and explore some techniques to utilize it in security applications. We first present the "SW-PUF" - basic building block of this thesis, a novel PUF design that measures processor chip ALU silicon biometrics in a manner similar to all PUFs. Additionally, it composes the silicon measurement with the data-dependent delay of a particular program instruction in a way that is difficult to decompose through a mathematical model. We then implement the proposed PUF to solve various security issues for applications such as Software Protection and Trusted Computing. We prove that the SW-PUF can provide a more robust root of trust for measurement than the existing trusted platform module (TPM). Second, we present the "Reversible SW-PUF", a novel PUF design based on the SW-PUF that is capable of computing partial inputs given its outputs. Given the random output signature of specific instruction in a specific basic block of the program, only the computing platform that originally computed the instruction can accurately regenerate the inputs of the instruction correctly within a certain number of bits. We then implement the Reversible SW-PUF to provide a verifiable computation method. Our scheme links the outsourced software with the cloud-node hardware to provide proof of the computational integrity and the resultant correctness of the results with high probability. Finally, we employ the SW-PUF and the Reversible SW-PUF to provide a trust attribute for data on the Internet of Thing (IoT) systems by combining data provenance and privacy-preserving methods. In our scheme, an IoT server can ensure that the received data comes from the IoT device that owns it. In addition, the server can verify the integrity of the data by validating the provenance metadata for data creation and modification.

Physically Unclonable Function (PUF) designs proposed in the recent literature vary widely in diverse characteristics such as hardware resource requirement, reliability, entropy, and robustness against mathematical cloning. Most of the standalone PUF designs suffer from either poor performance profile or unacceptable resource-overhead. We present a novel PUF design paradigm, termed as PUF Composition, that utilizes smaller PUFs as design building blocks to define a “Composite PUF” having larger challenge-space and superior performance profile at reasonable resource-overhead. A formal framework for PUF composition based on a probabilistic model has also been developed to enable the Composite PUF designer to have a-priori estimate of the relative qualities of several composite PUF options, without actually implementing them physically. The notion of PUF composition, and the probabilistic model developed for delay-PUFs, have both been validated using Ring Oscillator PUF (ROPUF) and Arbiter PUF (APUF) on Xilinx Spartan-3 Field Programmable Gate Array (FPGA).

Silicon based Physical Unclonable Functions (PUFs) are circuits which measure random variations of the manufacturing process to generate a secret. The quality of a PUF predominantly depends on its predictability and reliability. Available quality measures are not always sufficient and do not show the root cause for high predictability. This paper suggests entropy and joint entropy of certain views on PUFs and interprets the measures to show different design issues to a designer and to give a global measure for PUF quality. Simulation results for Arbiter PUF, Ring Oscillator PUF, and SRAM PUF are evaluated by the new measures and results for Ring Oscillator and Arbiter PUFs show how the measures can be used to guide designers.

Internet of Things (IoT) have broad and deep penetration into our society, and many of them are resource-constrained, calling for lightweight security protocols. Physical unclonable functions (PUFs) leverage physical variations of circuits to produce responses unique for individual devices, and hence are not reproducible even by their manufacturers. Implementable with simplistic circuits and operable with low energy, PUFs are promising candidates as security primitives for resource-constrained IoT devices. Arbiter PUF (APUF) and its variants are lightweight in resource requirements but suffer from vulnerability to machine learning attacks. To defend APUF variants against machine learning attacks, in this paper we investigate a challenge input interface, which incurs low overhead. Analytical and experimental studies were carried out, showing substantial improvement of resistance against machine learning attacks when a PUF is equipped with the interface, rendering interfaced APUF variants promising candidates for security critical applications.

Physical Unclonable Function (PUF) circuit extracts information from variations in a circuit or physical design to generate a unique key for electronics authentication, such as IoT devices and embedded systems. We proposed a high-speed pseudo linear feedback shift register with multiple ring oscillators PUF (PL-MRO-PUF), replacing the registers in LFSR with combinational logic to resemble a delay-sensitive ring oscillator (RO) circuit Furthermore, the use of multiple LFSR-based ROs with each different number of stages to form a 128-bit PUF allows us to increase the output's entropy and throughput. Hence, we have implemented the architecture in the Xilinx Artix-7 FPGA series boards. We have improved the operating frequency by 1.95×, and improve FoM by 1.5× compared to the PL-PUF [1]. We also have achieved higher randomness and uniqueness of 98.8% and 51.7%, respectively, compared to the conventional Arbiter PUF (A-PUF) [2].

The physical unclonable functions (PUFs) have been attracted attention to prevent semiconductor counterfeits. However, the risk of machine learning attack for an arbiter PUF, which is one of the typical PUFs, has been reported. Therefore, an XOR arbiter PUF, which has a resistance against the machine learning attack, was proposed. However, in recent years, a new machine learning attack using power consumption during the operation of the PUF circuit was reported. Also, it is important that the detailed tamper resistance verification of the PUFs to consider the security of the PUFs in the future. Therefore, this study proposes a new machine learning attack using electromagnetic waveforms for the XOR arbiter PUF. Experiments by an actual device evaluate the validity of the proposed method and the security of the XOR arbiter PUF.

Random numbers are widely used in cryptographic algorithms and protocols. A faulty true random number generator (TRNG) may open a door into a system in spite of cryptographic protection. It is therefore important to design TRNGs so that they can be tested at different stages of their lifetime to assure their trustworthiness. In this paper, we propose a method for designing physical unclonable function (PUF)-based TRNGs which can be tested in-field by known answer tests. We present a prototype FPGA implementation of the proposed TRNG based on an arbiter PUF which passes all NIST 800-22 statistical tests and has the minimal entropy of 0.918 estimated according to NIST 800-90B recommendations. This is a nontrivial achievement given that arbiter PUFs are notoriously hard to place in a symmetric manner in FPGAs.

Communication security is essential for the proper functioning of the Internet of Things. Traditional approaches that rely on cryptographic keys are vulnerable to side-channel attacks. Physical Unclonable Functions (PUFs), leveraging unavoidable and irreproducible variations of integrated circuits to produce responses unique for individual PUF devices, are emerging as promising candidates as security primitives to provide keyless solutions. Before a PUF can be adopted for real applications, the PUF must be thoroughly examined to understand its various properties for its application feasibility. In this paper, we study XOR PUFs for broad ranges of values for circuit architecture parameters. XOR PUFs have been extensively studied, and have been shown to be unable to withstand machine learning attacks for 64-bit XOR PUFs with less than ten component PUFs. Attack methods employed in existing studies need a large number of challenge-response pairs (CRPs), which are obtainable only if the PUF has an open access interface. When PUF-embedded devices equipped with mutual authentication or response obfuscating techniques, it is difficult for attackers to accumulate large numbers of CRPs. With only a small number of accumulated CRPs available to attackers, small size PUFs, like XOR PUFs with a small number of component PUFs and stages, may become resistant to machine learning attacks. Since smaller sizes mean less resource-demanding, it is worthwhile to examine such PUFs which have usually been considered unsafe against attacks. Such are thoughts that have been motivating us in this paper to explore the PUF performances for a wide range of values of the PUF architecture parameters.