17- https://doi.org/10.1109/iscas.2002.1009984
High-speed add-compare-select units using locally self-resetting CMOS
- Aug 7, 2002
- Gunok Jung +3 more
Abstract
This paper presents a new self-resetting CMOS design for an add-compare-select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMOS designs have also been implemented for comparison purposes. The simulation results show that, with the SRCMOS technique, the ACS units operate at a data rate of 568 Mbps in a 0.25 micron CMOS technology, as compared to 357 Mbps and 485 Mbps for static and domino CMOS implementations, respectively.
- # Static CMOS
- # Add-compare-select
- # Static CMOS Designs
- # Micron CMOS Technology
- # Domino CMOS
- # Key Building Block
- # Viterbi Decoder
- # CMOS Design
- # Two-phase Designs
- # Static Designs
