High-Speed AES Encryptor With Efficient Merging Techniques

In this study, Field Programmable Gate Array (FPGA) implementation of Conic Section Function Neural Network (CSFNN) for a classification problem focused on iris plant is presented. This work demonstrates for the first time to our knowledge, the feed-forward computation of CSFNN implementation on FPGA. Using l6-bit floating point arithmetic and the look-up tables (LUTs) for the sigmoid function and the square root function, 83% and 72% of slices and LUTs on Spartan 3-E XC3S1600E are used for the realization of CSFNN with five neurons. The classification results obtained from the FPGA implementation and software simulation show that the accuracy error between two platforms is only 0.1%.

This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

A single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm, Rijndael is presented. Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. The FPGA implementation described here is that of a fully pipelined single-chip Rijndael design which runs at a data rate of 7 Gbits/sec on a Xilinx Virtex-E XCV812E-8-BG560 FPGA device. This proves to be one of the fastest single-chip FPGA Rijndael implementations currently available. The high Block RAM content of the Virtex-E device is exploited in the design.KeywordsFPGA ImplementationAESRijndaelEncryption

In this paper we describe a single-node, double precision Field Programmable Gate Array (FPGA) implementation of the Conjugate Gradient algorithm in the context of Lattice Quantum Chromodynamics. As a benchmark of our proposal we invert numerically the Dirac–Wilson operator on a 4-dimensional grid on three Xilinx hardware solutions: Zynq Ultrascale+ evaluation board, the Alveo U250 accelerator and the largest device available on the market, the VU13P device. In our implementation we separate software/hardware parts in such a way that the entire multiplication by the Dirac operator is performed in hardware, and the rest of the algorithm runs on the host. We find out that the FPGA implementation can offer a performance comparable with that obtained using current CPU or Intel’s many core Xeon Phi accelerators. A possible multiple node FPGA-based system is discussed and we argue that power-efficient High Performance Computing (HPC) systems can be implemented using FPGA devices only.

This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

Small embedded systems, such as using a 16-bit CPU, are required to connect to the Internet. In addition, the systems are required to support encrypted communication. We develop a ubiquitous platform which supports Internet Protocol version 6 (IPv6) and IP Security (IPSec). This paper describes realization of Advanced Encryption Standard (AES) processing controlled by an original compact CPU core for small embedded systems. AES encryption and decryption processing requires CPU capability. AES accelerators for a Field Programmable Gate Array (FPGA) perform high speed execution, furthermore they require the resources of an FPGA. In order to conserve the resources of the FPGA, the basic operations of AES, SubBytes, ShiftRows and MixColumns transformation, are incorporated in each hardware module. The modules are controlled by the original compact CPU core. Moreover, the CPU core is designed for small embedded systems. The CPU core is able to support only instructions used in application software. Using the CPU core, AES processing is accomplished conserving FPGA resources, and is simply designed.

Encryption is the primary way for ensuring communication security. The symmetric key method, often known as Advanced Encryption Standard (AES), is a well-known technique in the field of security. AES can be implemented in either software or hardware. In the current study, Field Programmable Gate Arrays (FPGAs) are utilized to implement AES. Number of studies have been done on experiments of AES using FPGAs. Till date, no study has been done on the architectures that are being utilized to implement AES on FPGA. This paper provides an in-depth examination of several hardware implementation of AES on FPGA in terms of through put and performance. This survey article enables the engineers to choose the best architecture of FPGAs to implement AES algorithm in terms of design as per the requirement. The surveyed architectures are sequential, pipelined, iterative, and parallel. Parallel architectures with pipelining between rounds have shown an excellent throughput. Certain improved S-box and key expansion approaches have also been employed by the researchers to reduce the hardware areas.KeywordsAES algorithmAES architecturesPipeline architectureParallel architecture

Speed optimal FPGA implementation of the encryption algorithms for telecom applications

Characterisation of the standard deviation of a time‐series signal has uncommon, yet widespread applications. The usual requirement for a representation of signal standard deviation in real‐time implies a high computation speed. A method based on a field programmable gate array (FPGA) implementation is presented. The technique is benchmarked against conventional computational approaches and shows a single windowed standard deviation update calculation of a 16 bit sample can be achieved in 11 ns on a modern CPU. The FPGA implementation is found to be superior to all other approaches examined with an operation time of below 10 ns, and thus provides a useful tool for the real‐time measurement of the standard deviation of signals above 100 MHz.

High-speed FPGA implementation of orthogonal matching pursuit for compressive sensing signal reconstruction

Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

Closed-loop stimulation of many neurological disorders, such as epilepsy, is an emerging technology and regarded as a promising alternative for surgical and drug treatment. In this paper, a real-time seizure detection algorithm based on STFT and support vector machine (SVM) and its field-programmable gate array (FPGA) implementation are proposed. With a two-stage patient-specific channel selection and feature selection mechanism, those redundant and uncorrelated spectral features are removed from the entire feature set. The evaluation results on CHB-MIT epilepsy database show that the mean detection latency of the proposed algorithm is 6 s, the sensitivity is 98.4&#x0025;, and the false detection rate is 0.356/h. The performance of our proposed algorithm is comparable to other existing seizure detection algorithms. Moreover, we implement the proposed seizure detection algorithm on Xilinx Zynq-7000 XC7Z020 with high level synthesis. Each classification of the input electroencephalography signal can be finished within 313 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, and the power consumption of the programmable logic is only 380 mW at 100 MHz. In hardware implementation, an optimization strategy for the nested-loop structure within nonlinear SVM is proposed to improve pipeline efficiency. Compared with existing method, the experimental result shows that our method can speed up the nonlinear SVM by <inline-formula> <tex-math notation="LaTeX">$1.70\times $ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$1.53\times $ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$1.37\times $ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$1.26\times $ </tex-math></inline-formula> with the unroll factor equal to 1&#x2013;4 at the same DSP utilization rate. The evaluation results affirm the possibility of integrating the proposed algorithm and FPGA implementation into a wearable seizure control device.

Pseudorandom number generators (PRNGs) are fundamental components in cryptographic algorithms. The new concept of multi-PRNG introduced in this article consists of a unique generator capable of producing multiple streams of pseudorandom numbers. Multiscroll chaotic systems are known for generating multiple scrolls within a single attractor. With the aforementioned this article introduces a novel field-programmable gate array (FPGA) implementation of a multi-PRNG based on a multiscroll chaotic memristive Hopfield neural network (MHNN). The main contribution of this work is the generation of multiple spatially dependent PRNG streams from a chaotic multiscroll system by dividing the phase space of the attractor into sub-phase spaces. Each scroll in the multiscroll attractor functions as an independent PRNG. This innovative approach to generating multiple PRNGs from multiscroll chaotic systems is unprecedented in the existing literature. The 5-D MHNN chaotic model used in this work employs hyperbolic tangent and sine functions, which were implemented through a hardware-efficient CORDIC approach. Besides, The FPGA implementation to produce the chaotic time series leverages the Euler method with 32-bit fixed-point arithmetic, selected for its simplicity and low resource utilization. Finally, The randomness of the binary sequences produced by the multi-PRNG is rigorously validated using the NIST SP 800-22a and TestU01 suites, confirming their potential for cryptographic applications.

Sparse linear systems are commonly used in video processing applications, such as edge-aware filtering or video retargeting. Due to the 2-D nature of images, the involved problem sizes are large and thus solving such systems is computationally challenging. In this paper, we address sparse linear solvers for real-time video applications. We investigate several solver techniques, discuss hardware trade-offs, and provide field-programmable gate array (FPGA) architectures and implementation results of a Cholesky direct solver and of an iterative BiCGSTAB solver. The FPGA implementations solve 32 k × 32 k matrices at up to 50 f/s and outperform software implementations by at least one order of magnitude.

Most applications nowadays require protection of their data from tampering to ensure secure transfer of information. At the same time, they need to be secured quickly and within available resources. In this paper, efficient hardware architecture has been designed and implemented for the Advanced Encryption Standard (AES) algorithm based on the Field Programmable Gate Array (FPGA) using High Level Language (HLL). The design focused on the optimal use of available resources, thus iterative looping architecture is suggested to minimize the hardware resources utilization and power consumption. The design is synthesized and simulated using Xilinx ISE 14.7 and ModelSim software, respectively. The implementation is compared with other previous works in terms of area, and power consumption. The results show that the proposed design achieves significant decrease in area (utilize 423 slices) and power consumption (3.68 W). The throughput reaches the value of 2457 Mbit/Sec implemented on Virtex-6 xc6vlx195t-3 of Xilinx device family. This makes the proposed design suitable for applications, where resources are limited.