High-speed DRAM interface

Dynamic random access memory (DRAM) devices are used to handle data transfer to and from the microprocessors in a computer or server. Traditionally, the speed of the memory devices has lagged behind that of the microprocessors. With the advent of high-speed microprocessors such as Intel's Pentium 4 and AMD's Athlon, the speed of DRAM has also increased from below 100 MHz to near 1 GHz. At the same time, memory chip density has increased from 512 Kbit to 256Mb or higher. To package the new generation of high-density devices, new packaging technology such as chip scale package (CSP) is being applied to replace SOJ and TSOP packages. This paper reviews the progress in memory technology and its applications, including Synchronous Dynamic Random Access Memory (SDRAM), Rambus DRAM (RDRAM), and Double Data Rate (DDR) SDRAM. Packaging technology used for these devices, including conventional TSOP, stacked TSOP and chip scale packages such as μBGA and memory BGA (mBGA) for Rambus and DDR are discussed. The surface mount technology (SMT) manufacturing process of Dual In-line Memory Modules (DIMM) is described. Experimental results on solder printing and reflow profile condition optimization for the DIMM modules are discussed in detail by comparison of the resulting microscopic solder joint grain structures.

The new generations of dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM) technologies are contributing significantly toward increased system performance. Improvement in processing speed, however, can be hampered by inefficiency in both package performance and module-level interconnect. Furthermore, these high performance memory die have been designed with center bond pads rather than the peripheral bond format more common in earlier applications. The change in die layout, although challenging for traditional lead-frame package technology, has proved ideal for array packaging. The array format package with the die facing down furnishes a much shorter circuit path than lead-frame packaged die, minimizing the signal path between die and the printed circuit board (PCB) structure. For this reason, the developers of Rambus DRAM (RDRAM) and dual data rate (DDR) DRAM have found that array type packages enable optimized memory performance. To enable higher density memory, Tessera has developed a package stacking process the company has defined the “μZ™ Ball-Stack” package. The package technology is targeted for a variety of memory as well as multiple-function applications, however, to be widely adopted the ball-stack methodology must be subjected to extensive qualification and reliability testing.

With the improvement of Digital Signal Processor (DSP)’s ability to process data, the requirement for memory access is higher and higher. In order to ensure the real-time performance of data processing, multiple processing stages including scalar execution level, access memory level in DSP core and peripherals like debug, the Host Port Interface (HPI) in DSP system needs to fetch or store data from memory more quickly. To solve this practical problem, this paper introduces a multi-port memory interface (MPMI) based on Advanced eXtensible Interface 4 (AXI4) bus protocol, which can connect multiple access ports in DSP system with Double Data Rate 4 (DDR4) Synchronous Dynamic Random Access Memory (SDRAM). The design has successfully passed the verification of various reading and writing scenarios, and the novel combination of fixed and polling priority makes the interface’s access efficiency increase by 32% compared with the one using a normal polling priority.

High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) has emerged as a preferred choice for leading-edge graphics, networking and highperformance computing applications. HBM is also finding usage in artificial intelligence (AI), machine learning (ML) and other advanced applications that demand high bandwidth and high power efficiency. HBM systems are implemented in 2.5D technology in which the memory stack and System-on-Chip (SoC) are integrated using a silicon interposer in a single package. Unlike conventional Double Data Rate (DDR) systems, the memory channel in 2.5D HBM systems are not accessible outside the package, posing multiple challenges in post-silicon characterization, system validation and SoC bring up. This paper discusses the functional at-speed test challenges and solutions using IEEE1500 based test structures implemented in the PHY, complementing those in DRAM. The paper also discusses a novel method to allow channel pin access for receiver and transmitter characterization with minimal impact to normal operation. Silicon results are presented at different levels of system hierarchy that consists of Memory Controller (MC), Physical Layer (PHY) and DRAM. Together, these results demonstrate excellent test coverage of the complete HBM memory subsystem and efficient silicon debug support.

Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array testing. Thus, it is inefficient to realize it using the dedicated BIST hardware. On the other hand, it is not time efficient if we use the processor (software) to execute the DRAM array testing. Therefore, the SHC-BIST scheme uses a programmable BIST circuit to execute the DRAM array testing and takes advantage of the processor to execute the DRAM initialization and control the programmable BIST circuit such that the test time and hardware cost can be minimized. We verify the SHC-BIST scheme using a system with a LEON3 processor and a multi-channel DRAM.

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

In order to realize real-time and high-speed distortion removal of camera images, a new improved high resolution and high frame rate image distortion based on FPGA is proposed. The traditional method uses four random access memory (RAM) to buffer the distorted image respectively, and then remaps it with the double rate synchronous dynamic random access memory (DDR), which will cause the system to be unable to process high-resolution images at high frame rates. A new RAM buffer architecture and an interpolation module more suitable for Field Programmable Gate Array (FPGA) implementation are proposed, which can improve the system’s ability to process high-speed and high-resolution distorted images in real time within the acceptable range of resources. Compared with the traditional FPGA de-distortion algorithm, the proposed method can de-distortion with the frame rate of 100 fps and the resolution of 3072 x 2048 x 8bit.

A highly efficient Synchronous Dynamic Random Access Memory (SDRAM) controller supporting variable-length burst access and batch process for discrete reads is proposed in this paper. Based on the Principle of Locality, command First In First Out (FIFO) and address range detector are designed within this controller to accelerate its responses to discrete read requests, which dramatically improves the average Effective Bus Utilization Ratio (EBUR) of SDRAM. Our controller is finally verified by driving the Micron 256-Mb SDRAM MT48LC16M16A2. Successful simulation and verification results show that our controller exhibits much higher EBUR than do most existing designs in case of discrete reads.

After analyzing the principle of SDRAM,a Synchronous Dynamic Random Access Memory(SDRAM) controller used in large-array CCD image real-time display system was designed with parameterization design concept.It was implemented by VHDL hardware description language and had a simple interface.Then the SDRAM controller was successfully used in real-time display system of large-array CCD image and worked very well.

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding “1”. The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading “1” to reading “0” (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

A complex modern embedded system using a multi-core Central Processing Unit (CPU) toward a compact integrated design in a single Printed Circuit Board (PCB). One of the biggest challenges of the design is to meet the Signal Integrity for high speed Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3) bus. A typical strategy to solve the challenge is the simulation on the computer, but this is not always an effective solution as has a gap between simulation software and practical PCB. The gap is correlated to localized changes in copper density within the PCB and characterization of heterogeneous materials in PCB that could lead to differences in the real PCB. The purpose of the research presents an analysis methodology to design DDR) memory interfaces in high speed embedded systems, related to Signal Integrity and the impact of copper density on PCB trace impedances to overcome these challenges. Moreover, the presented design methodology is also applied to the next generation DDR as well as other styles of CPU.

Dynamic random access memory (DRAM) is facing the challenge of technology scaling. The de-creasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hold data for a long time, DRAM chips need a more frequent refreshing operation. There-fore, in the near future, time and energy cost on DRAM refreshing will be no longer trivial. In this paper, we propose DRAM Error Correction Pointer (ECP), an error-correction-manner framework, to reduce DRAM re-freshes without data loss. We exploit the non-uniform feature of DRAM cells with respect to the data retention time. Compared with the conventional refreshing mechanisms, which refresh DRAM chips by the retention time of the leakiest cells, we refresh the chips much fewer times, and treat the not-in-time refreshed cells as fault elements. We use the structure of ECP as a fault tolerant element. By recording the data which are supposed to be written into the leaky cells in our DRAM-ECP structures, DRAM-ECP can significantly decrease refreshing frequency. When these data are to be read out, DRAM-ECP retrieves the data stored in ECPs and covers them to the corresponding position in the data row. Our experiments show that DRAM-ECP can reduce over 70% refreshing operations than the current refreshing mechanism and also get significant energy saving.

As one of the cornerstones of computing, dynamic random-access memory (DRAM) is prevalent across digital systems. Over the years, researchers have proposed modifications to DRAM macros or explored alternative uses of existing DRAM chips to extend the functionality of this ubiquitous media. This work expands on the latter, providing new insights and demonstrating new functionalities in unmodified, commodity DRAM. FracDRAM is the first work to show how fractional values can be stored in off-the-shelf DRAM. We propose two primitive operations built with specially timed DRAM command sequences, to either store fractional values to the entire DRAM row or to masked bits in a row. Utilizing fractional values, this work enables more modules to perform the in-memory majority operation, increases the stability of the existing in-memory majority operation, and builds a state-of-the-art DRAM-based PUF with unmodified DRAM. In total, 582 DDR3 chips from seven major vendors are evaluated and characterized under different environments in this work. FracDRAM breaks through the conventional binary abstraction of DRAM logic, and brings new functions to the existing DRAM macro.

Dynamic random access memory (DRAM) is used as the main memory in every personal computer, due to its high density, high speed and efficient memory function. The ever-shrinking dimensions of DRAM cells with increasing packing density made the cell's capacitor size to be smaller. For successful operation of DRAM, a large cell capacitance (~ 25 fF) and low leakage current (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> or 1 fA/cell) are required. In a traditional Si-based capacitor, the target cell capacitance has been achieved by increasing the surface area of the capacitor. More recently, innovations have been made by development of the component materials. A metal electrode, TiN or Ru, and a dielectric material with a moderate-k value (k is the relative dielectric constant), such as HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (k ~ 25) and ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (k ~ 40), are being explored in giga-bit scale DRAMs. The minimum achievable t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> is ~ 0.7 nm for ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> which is being used currently in DRAM industry. However, the technology road map for memory devices states that t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> of less than 0.45 nm is necessary for the DRAMs with a design rule of <; 20 nm. Perovskite-based dielectric films such as SrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (STO) and (Ba, Sr)TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> were reported to exhibit k values of several hundreds. However, growth of these films showed very slow growth rate and much more complicated processes than growth of binary oxide with the atomic layer deposition (ALD) technique which is a method of choice for the growth of the dielectric films and electrodes in microelectronic devices. Therefore, material and process innovations are necessary for next generation DRAM capacitors.

Dynamic Random Access Memory (DRAM) is widely used for data storage and, when a computer system is in operation, the DRAM can contain sensitive information such as passwords and cryptographic keys. Therefore, the DRAM is a prime target for hardware-based cryptanalytic attacks. These attacks can be performed in the supply chain to capture default key mechanisms enabling a later cyber attack or predisposition the system to remote effects. Two prominent attack classes against memory are the Cold Boot attack which recovers the data from the DRAM even after a supposed power-down and Rowhammer attack which violates memory integrity by influencing the stored bits to flip. In this paper, we propose an on-chip technique that obfuscates the memory addresses and data and provides a fast detect-response to defend against these hardware-based security attacks on DRAM. We advance the prior hardware security research by making two contributions. First, the key material is detected and erased before the Cold Boot attacker can extract the memory data. Second, our solution is on-chip and does not require nor depend on additional hardware or software which are open to additional supply chain attack vectors. We analyze the efficacy of our scheme through circuit simulation and compare the results to the previous mitigation approaches based on DRAM write operations. Our simulation and analysis results show that purging key information used for address and data randomization can be achieved much faster and with lower power than with typical DRAM write techniques used for sanitizing memory content. We demonstrate through circuit simulation of the key register design a technique that clears key information within 2.4ns which is faster by more than two orders magnitude compared to typical DRAM write operations for 180nm technology, and with a power consumption of 0.15 picoWatts.