High-stability adaptive frequency comparison method based on fuzzy area characteristics

Direct Digital Synthesizer (DDS) systems play a critical role in high-precision signal generation for applications like medical imaging and RF communications. This research explores the development of a DDS system using Field-Programmable Gate Array (FPGA) technology, with a focus on optimizing signal accuracy, resource efficiency, and signal-to-noise ratio (SNR). The study implemented two DDS designs on an FPGA: one based on the CORDIC algorithm and the other using a Look-Up Table (LUT) approach. Key components of the system included a phase accumulator, phase register, and frequency calculation algorithms. The system's performance was evaluated by measuring signal output accuracy and SNR, utilizing the ISL6961IAZ DAC and RF Transformers PWB2010LC for signal conversion and transmission. The results showed that the DDS achieved near-target frequencies, with outputs of 100.4 kHz for a target of 100 kHz and 498.8 kHz for a target of 500 kHz. The LUT-based design demonstrated superior signal fidelity, achieving an SNR of 106 dB compared to 92 dB for the CORDIC-based design. However, resource utilization analysis revealed a trade-off between logic efficiency and memory usage: the CORDIC design consumed 26% of logic elements and only 1% of memory, while the LUT-based design used 8% of logic elements and 77% of memory. These findings highlight the importance of balancing design choices based on application-specific requirements for precision, resource constraints, and performance.

This article discusses the current state and development trends of microwave frequency synthesizers for test-and-measurement instruments. The discussed trends are also applicable for other synthesizer types used as modules in more complex systems. Test-and-measurement synthesizer market is estimated at $300 with an annual growth rate about 3%.A modern trend for the development of frequency synthesizers is associated with low phase noise, low spurious and fast switching speed. Important parameters also include operating frequency range, frequency resolution, modulation capabilities as well as size and cost characteristics. The main architectures based on direct analog, direct digital and indirect synthesis are evaluated. As of today, traditional indirect phase-lock-loop (PLL) architectures still dominate. On the other hand, direct analog synthesis is the most advanced approach that demonstrates extremely fast switching speed and low phase noise. Nevertheless, future developments are associated with direct digital synthesis (DDS) due to the rapid progress in solid-state technologies. DDS are currently available as special integrated circuits (IC) or can be build using field-programmable logic arrays (FPGA) and high-frequency digital-to-analog converters (DAC). Parallel (multichannel) digital structures coupled with high-frequency DACs allow generating output signals at microwave frequencies. Further improvements are possible using two or more DACs in an interleaved data mode. Wider frequency coverage through several tens of gigahertz and lower spur characteristics are expected.The article notes that modern frequency synthesizers allow generating complex signals using vector IQ-modulation. The modulation bandwidth is constantly increases through hundreds of megahertz or even several gigahertz. Further advances in microwave frequency synthesizers are associated with new reference types such as sapphire-loaded cavity oscillators with combined frequency stabilization as well as optoelectronic methods.

Building the machines that advance scientific knowledge is one of the most significant challenges of our time. So-called Big Science instruments are unique; the expertise required to build them is multidisciplinary, and few countries can build and maintain them. Since resources and budgets are not unlimited, these require efficient solutions. Big Science machines take a decade to plan, a decade to build, and at least a decade to operate. One such machine is the largest fusion reactor project, ITER, which promises to be the next step in fusion research and has a big challenge in system integration. To mitigate the integration effort, ITER has invested in standardization, both in software and hardware, introducing standard instrumentation software named Nominal Device Support (NDSv3); Micro Telecommunication Computing Architecture (MTCA) as the long-term hardware standard choice, and EPICS as a general-purpose distributed control system. These control systems are essential in the management of the facility. They provide functions such as communication protocols, process management, monitoring, alarms, and human-machine interfaces. But also, more advanced access to databases or data acquisition systems. The latter is typically managed by a Field Programmable Gate Array (FPGA), of which facilities can easily have thousands of these FPGAs managing millions of signals within the control system environment. Nevertheless, these FPGA data acquisition (DAQ) systems continue to be labor-intensive. Standardized, modular, and open-source frameworks have been proposed to solve this problem, however, the FPGA programming expertise requirement remained. This thesis proposes a complete technology stack that considers these DAQ systems from the control system to the hardware. It provides a methodology using the Open Computing Language (OpenCL) to reduce the FPGA programming effort. The FPGA devices are programmed using C/C++-like environments, which are much simpler than traditional Hardware Description Languages (HDLs). The software, named IRIO-OpenCL, is written in C++ following ITER's NDSv3 model, which abstracts and generalizes the development of software device drivers and simplifies the interface to EPICS. IRIO-OpenCL is specifically designed to simplify the integration of intelligent instrumentation systems, allowing the integration of algorithms into the FPGA without modifying large parts of the supporting library. The MTCA standard was chosen to maintain modularity. The chassis backplane connects to the devices via Ethernet and PCIe, enabling standard communications. The Advanced Mezzanine Card is the typical MTCA FPGA-based DAQ carrier board. It connects the FPGA to the chassis backplane and typically provides FPGA Mezzanine Connectors (FMCs) for plugging in analog-to-digital (ADC) carrier boards. An ADC connected via the FMC interface samples the analog signals passed to the OpenCL processing kernels. Using OpenCL, the FPGA kernels communicate with the host machine in a standardized way. To demonstrate the applicability of this methodology, reference problems were selected from the literature and implemented, both with traditional and deep learning (DL) solutions. The methodology elaborates on connecting the OpenCL kernels for any use case, and the results show examples of kernel sets. The neutron flux measurement problem is solved at 1GS/s in real time using pulse counting and Campbell techniques, using 40% of the target Arria10 FPGA. The DL application example is based on a neutron/gamma discrimination neural network (NN) that achieves a classification rate of up to 1.3 MEvents/s using less than 25% of the target resource. RESUMEN Construir máquinas que avancen el conocimiento científico es uno de los desafíos más significativos de nuestro tiempo. Los instrumentos de la llamada Big Science son únicos; las competencias requeridas para su construcción son multidisciplinares, y pocos países pueden construirlos y mantenerlos. Dado que los recursos y presupuestos no son ilimitados, estos requieren soluciones eficientes. Las máquinas de Gran Ciencia tardan una década en planificarse, una década en construirse y al menos una década en operarse. Una de estas máquinas es el proyecto del reactor de fusión más grande, ITER, que promete ser el siguiente paso en la investigación de fusión y presenta un gran desafío en la integración de sistemas. Para mitigar el esfuerzo de integración, ITER ha invertido en estandarización, tanto en software como en hardware, introduciendo un software de instrumentación estándar llamado Nominal Device Support v3 (NDSv3); Micro Telecommunication Computing Architecture (MTCA) como la elección estándar de hardware a largo plazo, y EPICS como un sistema de control distribuido de propósito general. Estos sistemas de control son esenciales en la gestión de la instalación ya que proporcionan funciones como protocolos de comunicación, gestión de procesos, monitorización, alarmas e interfaces de usuario, además de acceso avanzado a bases de datos o sistemas de adquisición de datos. Este último es típicamente gestionado por un Field Programmable Gate Array (FPGA), de los cuales las instalaciones pueden tener fácilmente miles de unidades gestionando millones de señales dentro del entorno del sistema de control. Estos sistemas de adquisición de datos (DAQ) con FPGA siguen requiriendo programación experta y laboriosa. Se han propuesto marcos estandarizados, modulares y de código abierto para resolver este problema, sin embargo, la necesidad de experiencia en programación FPGA no se ha podido eludir. Esta tesis propone una pila de tecnologías que considera estos sistemas DAQ desde el sistema de control hasta el hardware. Proporciona una metodología utilizando el Open Computing Language (OpenCL) para reducir el esfuerzo de programación FPGA. Los dispositivos FPGA se programan utilizando entornos similares a C/C++, que son mucho más simples que los Lenguajes de Descripción de Hardware (HDL) tradicionales. El software, llamado IRIO-OpenCL, está escrito en C++ siguiendo el modelo de NDSv3 de ITER, que abstrae y generaliza el desarrollo de controladores de dispositivos de software y simplifica la interfaz con EPICS. IRIO-OpenCL está específicamente diseñado para simplificar la integración de sistemas de instrumentación inteligentes, permitiendo la integración de algoritmos en el FPGA sin modificar grandes partes de la biblioteca de soporte. El estándar MTCA fue elegido para mantener la modularidad. El backplane del chasis se conecta a los dispositivos a través de Ethernet y PCIe, habilitando comunicaciones estándar. La Advanced Mezzanine Card es la placa portadora DAQ FPGA típica de MTCA, que conecta el FPGA al backplane del chasis y típicamente proporciona FPGA Mezzanine Connectors (FMC) para conectar placas con conversores analógico-digitales (ADC). Un ADC conectado a través de la interfaz FMC muestrea las señales analógicas pasadas a los núcleos de procesamiento OpenCL. Utilizando OpenCL, los núcleos FPGA se comunican con la máquina anfitriona de una manera estandarizada. Para demostrar la aplicabilidad de esta metodología, se seleccionaron e implementaron problemas de referencia de la literatura, tanto con soluciones tradicionales como de Deep Learning (DL). La metodología elabora ejemplos de conexión de núcleos OpenCL para cualquier caso de uso, y los resultados muestran ejemplos de conjuntos de núcleos. El problema de medición del flujo de neutrones se resuelve a 1GS/s en tiempo real utilizando técnicas de conteo de pulsos y Campbell, utilizando el 40% del objetivo FPGA Arria10. El ejemplo de aplicación DL se basa en una red neuronal para la discriminación neutrones/gammas que logra una tasa de clasificación de hasta 1.3 MEventos/s utilizando menos del 25% de la FPGA objetivo. LABURPENA Ezagutza zientifikoa aurreratzen duten makinak eraikitzea gure garaiko erronka garrantzitsuenetako bat da. Big Science deritzonaren makinak bakarrak dira; beharrezko esperientzia diziplina anitzekoa da, eta herrialde gutxik eraiki eta mantendu ditzakete. Baliabideak eta aurrekontuak mugagabeak ez direnez, konponbide eraginkorrak behar dira. Zientzia Handi makinak hamarkada bat behar dute diseinatuak izateko, hamarkada bat eraikitzeko eta gutxienez hamarkada bat jarduteko. Makina horietako bat fusio-erreaktore handienaren proiektua da, ITER, fusio-ikerketan hurrengo urratsa izango dena eta sistemak integratzeko erronka handia aurkezten duena. Integrazio-ahalegina arintzeko, ITERek estandarizazioan inbertitu du, bai softwarean bai - eta EPICS helburu orokorreko kontrol-sistema banatua. Kontrol-sistema horiek funtsezkoak dira instalazioa kudeatzeko. Komunikazio-protokoloak, prozesuen kudeaketa, monitorizazioa, alarmak eta pertsona-makina interfazeak bezalako funtzioak ematen dituzte, datubaseetarako edo datuak eskuratzeko sistemetarako sarbide aurreratua izateaz gain. Azken hori "Field Programmable Gate Array" (FPGA) batek kudeatzen du, milaka FPGA konektatuz makina bakoitzean eta kontrol-sistemaz milioika seinale kudeatuz. FPGA duten datuak eskuratzeko sistemek (DAQ) programazio aditua eta neketsua eskatzen jarraitzen dute. Problema hori ebazteko marko estandarizatuak, modularrak eta kode irekikoak proposatu dira, hala ere, FPGA hardware programazio espezializatuaren beharra ezin izan da ukatu. Tesi honek DAQ sistema hauek kontrol sistematik hardwareraino kontsideratuz teknologia bilduma bat programazio-ahalegina murrizten du. FPGA gailuak C/C++ antzeko inguruneak erabiliz programatzen dira, - OpenCL izenekoa, C++n idatzita dago, ITERren "Nominal Device Support v3" (NDSv3) eredua jarraituz. Honek software-gailuen garapena diseinu abstraktu eta orokorrez EPICSekiko interfazea sinplifikatzen du. IRIOOpenCL berariaz diseinatuta dago instrumentazio-sistema adimendunen integrazioa sinplifikatzeko, eta algoritmoak FPGAn integratzea ahalbidetzen du, software zati handiak aldatu gabe. Modularitateari eusteko, MTCA estandarra aukeratu da. Txasisaren backplanea Ethernet eta PCIe bidez konektatzen da gailuetara, komunikazio estandarrak gaituz. "Advanced Mezzanine Card" MTCAren ohiko DAQ FPGA plaka eramailea da. FPGA txasisaren backplanera konektatzen du eta, normalean, "FPGA Mezzanine Connectors"ak (FMC) ditu plaka bihurgailu analogiko-digitalak (ADC) konektatzeko. ADCak, FMC interfazearen bidez konektatuta, OpenCL prozesatze-nukleoetara igarotako seinale analogikoak bihurtzen ditu. OpenCL erabiliz, FPGA nukleoak ordenagailuarekin modu estandarizatuan komunikatzen dira. Metodologia horren aplikagarritasuna egiaztatzeko, erreferentziazko adibideak literaturatik hautatu eta nukleoen konexio-adibideak egiten ditu, edozein kasutan erabiltzeko, eta emaitzek nukleo multzoen adibideak erakusten dituzte. Neutroi-fluxuaren neurketak 1GS/s-ko ebazten dira real time errendimenduaz, pultsuak eta Campbell zenbatzeko teknikak erabiliz, Arria10 FPGAren % 40 erabiliz. Azkenik, DL aplikazioaren adibidea, neutroi/gamma sailkapena, sare neuronal batean oinarritzen da, eta FPGAren baliabideen % 25 baino gutxiago erabiliz 1.3 MSailkapen/s sailkapen-tasa lortzen du.

In this study, an ongoing Project named FPGA Based Digital Electronics Education (FPGA_b_DEEP) is introduced and the advantages of FPGA(Field Programmable Gate Arrays) technology which brought to digital design area are dealt with by using a case study. The Project aims to develop instructive and attractive examples to teach Digital Electronics efficiently and faster. In addition to this, PBL(Project Based Learning) method and Micro Learning method are dealt with at the study separately. PBL method has been used partially at the Project and the studies on Micro Learning for association with the Project are going on recently.

This paper presents a digital implementation of 4-D autonomous hyperchaotic system on a Field Programmable Gate Array (FPGA) technology. In the design, the system parameters are selected according to the requirements for obtaining a hyperchaotic behavior. The hyperchaotic nature is theoretically verified by using bifurcation analysis and Lyapunov exponents’ calculus; and experimentally assessed by the FPGA implementation. A master-slave scheme for secure data transmission is used. Active control is applied to carry out the synchronization between the master and the slave. FPGA technology is applied in order to be implemented in digital form the 4-D continuous system using a XILINX VERTEX5 chip. The digital sequence generated from the FPGA device is observed in our experimental setup. The implementation with 32 bits fixed point is chosen; highlighting the role of synchronization mechanisms of chaotic systems in the success of these transmissions.

Various modulation techniques are usually utilized to enhance the radar performance, or to add more capabilities to the radar that otherwise would not have been possible. Digital generation methods of frequency modulated continuous wave signals include direct waveform synthesis and frequency synthesis. The implementation of waveform generation and upconversion method are described in this paper with a simplified digital implementation technique using FPGAs (Field Programmable Gate Array). The design follows a systematic approach following steps of timing generation from external encoder, baseband modulated waveform generation, upconversion of the waveform to intermediate frequency, filtering and finally frequency synthesis using external DDS (Direct Digital Synthesizer). The design is also capable of generating BITE waveform for test checking in the system. Our design is capable of generation of waveform for stationary as well as non-stationary radars. For non-stationary radars, the waveform is so generated that the doppler effect due to the movement of the radar is compensated. The paper explains more on this. This work mainly focuses on the fact that the total design has been implemented on a single FPGA and the implementation solution utilizes the efficient FPGA resources so as to meet the timings in crucial applications. Moreover, the paper enhances the features of the design with simulation and real time results used to validate the design.

The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

In a radar application, Time Signal Generator (TSG) is used to generate timing and control signals which helps radar to operate in different functions. The functions include tracking, detection, and hold mode. Timing Signal Generator is the heart of radar applications. Timing Signal Generator is the main part of radar application, which is responsible for synchronization between Transmitter and receiver for the transmitted signal. In this work, an implementation of timing signal using a Hardware Description Language (HDL) language-based state machine which is responsible for enabling Direct Digital Synthesis and Analog to Digital Converter in the Transmitter and receiver window. Timing Signal Generator implementation on Field Programmable Gate Array is preferred as the entire Timing signal generator unit can be assembled on a single Field programmable gate array chip, and conditional modification can be performed remotely, which is cost-effective. Timing signal generator generation begins by providing an arbitrary frequency and phase signal configuration to DDS-AD9854 from Field programmable gate array. Direct digital synthesis block generates a single-tone signal and Binary Phase Shift Keying signal and a chirp signal based on an input arbitrary signal sent by ZYBO-7010 FPGA.

Rail inspection is the most important maintenance method for the safety of rail transportation. With the advantages of noncontact inspection, electromagnetic tomography can be an ideal technique to realize online inspection. In this paper, a novel Electromagnetic Tomography rail inspection prototype developed with Field Programmable Gate Array(FPGA) as front circuit control and signal demodulation unit. The rail inspection sensor designed with 12 coils matrix formed as “L” shape to meet the wheel and track running condition. In the sensor matrix four excitation coils are excited by four individual direct digital synthesizer(DDS) implemented by FPGA. Four signals with four optimized frequencies applied simultaneously to excite four tomographic projection. Other coils pairs in the array are acting as detection coils to measure response signals at the same time. This excitation strategy makes the four projection of electromagnetic tomography applied parallel to improve the efficiency of inspection. The measurement coils' output signals demodulated by FPGA in real time and then the demodulation results are transferred to an image reconstruction computer with user diagram protocol(UDP) by Ethernet. Linear Back Projection image reconstruction algorithm used to reconstruct the rail defect to meet the construction speed requirement. Rail inspection experiments show that the prototype is feasible to be used in real time rail inspection.

There exist a number of algorithms to map the phase to amplitude in direct digital synthesis (DDS). For DDS with more than 14 output bits, the Coordinate Rotation Digital Computer (CORDIC) algorithm is well known for its high precision. Also, it is effective in solutions where there is the need of in-phase and quadrature components simultaneously because the algorithm calculates both. In this paper, a Taylor expansion based method was proposed to calculate both in-phase and quadrature at the same time. Numerical simulations for different data format, e.g., double and finite bits, were carried out in Matlab and Quartus, which were followed by the hardware implementation in Field Programmable Gate Array. The results demonstrated that the proposed method possessed higher precision and exhausted less logic elements than the CORDIC algorithm.

<p>This Master’s thesis consists of the development of a Nuclear Magnetic Resonance (NMR) Radio Frequency (RF) transmitter, which is a core electronic subsystem of an NMR system. The main purpose of this research is to contribute to the application of NMR, which is a new sensing technology that has yet to be fully implemented into the everyday world. One of the barriers to adopting this technology is its complexity. However, the invention of high speed digital FPGAs (Field Programmable Gate Array) such as the Spartan series has made it easier to develop high performance NMR systems over recent years. The major contribution to this research is the development of faster digital signal processing hardware, and methodologies that have been implemented on a single chip. This has reduced the size and the cost of the electronic subsystem and contributed towards the evolution of NMR as a general tool. This thesis introduces the concept of implementing a high-speed NMR RF multi-frequency transmitter by using multiple Direct Digital Synthesis (DDS) cores to generate sine-waves, which range from 100 kHz to 750 MHz. The research required three stages to be achieved, beginning with conceptual design of a high-speed transmitter using MATLAB-Simulink, RTL-level (Register-Transfer Level) simulation and hardware implementation, which included hardware testing on a prototype board. This Master’s research is to seek a solution to building a multi-core DDS module in an FPGA device. In other words, the research work focuses on finding an alternative solution to constructing a DDS system. The project involves building up the VHSIC Hardware Description Language (VHDL) program to work beyond the hardware limitation of an FPGA device. Hence, the final solution does not consider any noise impact due to the structure of the developed system.</p>

Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is to design prototype of an input/output port with handshaking capability using Field Programmable Gate Array (FPGA). The main reason of using the FPGA technology is it has unlimited number reprogrammed, cuts developing cost and development time. Xilinx Foundation 2.1i Series software in VHDL description was used as a development tool in this project. The VHDL codes were assimilated into a design and development atmosphere to accomplish many subtasks such as FPGA synthesis, optimization, placement, and routing. The successful design was translated, mapped, routed, and placed onto FPGA Demo Board. XC4010XLPC84 Xilinx FPGA from XC4000XL family was used as a target board. In prototype design, the FPGA pins were connected to a parallel printer port by using a coupled 25-pin DB connector, with a 36-pin Centronics connector cable. The output signals were observed and analyzed by using a logic analyzer.

Binary Phase codes such as barker codes are widely used in radar pulse compression processing. Most of the radar signal processing applications use pulse compression codes to improve the range resolution. This can be achieved by phase codes such as barker codes and nested barker codes with reduced sidelobes. A field programmable gate array (FPGA) with low cost hardware architecture can be used effectively to implement these pulse compression codes. This paper proposes a novel approach to implement binary phase or barker codes and nested barker codes using a direct digital synthesizer and system generator which is a token of MATLAB Simulink Xilinx block set. The generated binary codes further tested and implemented on FPGA ZYNQ board (ZC7045-2ffg900) extensively used in radar signal processing.KeywordsBarker codesNested barker codesDirect digital synthesizerNested barker codeHardware co-simulation

The range resolution and target detection capability in Radar Pulse compression techniques can be improved efficiently by a Linear frequency modulated (LFM) waveform or a chirp signal. As the conventional method of generating Linear frequency modulated waveform causes several limitations like instability and nonlinearity, this paper has proposed a digital technique to generate LFM signal by using a multi-DDS approach. For hardware implementations of any digitally designed module, the Joint Test Action Group (JTAG) plays a vital role in real-time processing. The JTAG standards in Field Programmable gate arrays (FPGA) are allowed to debug any design with the help of Hardware Co-Simulation JTAG block. In this paper, a linear frequency modulated waveform is generated using a Direct Digital Synthesizer (DDS) and System generator Xilinx block set. The Generated chirp signal is further implemented on FPGA-ZYNQ board (ZC7045-2ffg900), by generating a Hardware Co-simulation JTAG block, essentially required for radar signal processing.

This paper presents an approach for the mismatch pulse compression implementation in spread spectrum radars with binary phase intra-pulse modulated pulses. Design and verification of the matched and mismatched filter for signals coded by Barker and M sequences are accomplished on a digital radar signal synthesis and processing platform based on direct digital synthesis (DDS) and field programmable gates array (FPGA) technology. Coefficients of mismatched filters are obtained by DIRLS algorithm with 16-bit resolution. The compressors are verified with sequences lengths of 13 and 31, and bandwidth of 3.3 MHz.