High Throughput Asynchronous NoC Design under High Process Variation

This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

Homogeneous manycore processors are emerging in broad application areas, including those with timing requirements, such as real-time and embedded applications. Typically, these processors employ Network-on-Chip (NoC) as the communication infrastructure and core-level redundancy is often used as an effective approach to improve the yield of manycore chips. For a given application's task graph and a task to core mapping strategy, the traffic pattern on the NoC is known a priori. However, when defective cores are replaced by redundant ones, the NoC topology changes. As a result, a fine-tuned program based on timing parameters given by one topology may not meet the expected timing behavior under the new one. To address this issue, a timing similarity metric is introduced to evaluate timing resemblances between different NoC topologies. Based on this metric, a Hungarian method based algorithm is developed to reconfigure a defect-tolerant manycore platform and form a unified application specific virtual core topology of which the timing variations caused by such reconfiguration are minimized. Our case studies indicate that the proposed metric is able to accurately measure the timing differences between different NoC topologies. The standard deviation between the calculated difference using the metric and the difference obtained through simulation is less than 6.58%. Our case studies also indicate that the developed Hungarian method based algorithm using the metric performs close to the optimal solution in comparison to random defect-redundant core assignments.

Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.

Photonic integrated networks on chip (NoC) can exploit wavelengths enabling parallelism in data communications between the processors and memory elements of computing systems. A suitable scheduler is, however, required to achieve uniformly low latency and high throughput. In this paper, the performance of a two-step scheduling framework addressing the matching and wavelength assignment problem is compared in two different NoC topologies: unidirectional ring and bus, having both a limited number of wavelengths. Latency results show that the ring is slightly outperforming the bus, thanks to a better balance of the link load. Also, tunability of laser sources enables significant latency reduction. However, the complexity associated with tunability control can be avoided using two transceivers per node.

The network-on-chip(NoC) is one of important aspects in digital circuit design, it attracted more and more attentions in electronic engineering. The NoC has been proposed as a promising solution to act as communication architecture because the number of cores in the systems-on-chip(SoC) is increased greatly. A lot of work needs to be carried out in the design of NoC, such as the determinations of the NoC communication backbone and communication protocols, the allocation of cores to various available nodes in NoC topology, that is the core mapping. The task of core mapping is to determine the topological placement of cores onto the nodes in NoC topology structure, and choose a path for each pair of IP cores. In this paper, the NoC structure with mesh topology is considered, a new approach is presented for the core mapping of network-on-chip by using Tabu search algorithm. The evolution operations in genetic algorithms are added to the Tabu search process to enhance the computation efficiency. The experimental results show that the time being needed to obtain the core mapping scheme by the approach proposed in this paper is lower than conventional genetic algorithm.KeywordsDigital circuitsnetwork-on-chipscore mappingTabu search algorithmgenetic algorithms

Leakage power is a paramount concern in the design of Field Programmable Gate Arrays (FPGAs), and process variations have aggravated the problem. At the 45 nm technology node and beyond leakage variations can diminish the power yield of a design. To handle the increased complexity of the state-of-the-art designs, FPGAs have been scaled in size and complexity, leading to increased leakage, and more variation in leakage power. In this paper impact of process variations on the leakage in FPGAs is analyzed and variability aware CAD algorithms for mitigating the impact of process variations are developed. A programmable dual-Vdd FPGA architecture is selected on which these algorithms are implemented to evaluate the improvement in the power yield of FPGAs. The results indicate that the proposed CAD technique leads to 3%-9% improvement in the power yield.

Networks-on-chip (NoC) have been widely proposed as the future communication paradigm for use in next-generation system-on-chip. In this paper, we present NoCOUT, a methodology for generating an energy optimized application specific NoC topology which supports both point-to-point and packet-switched networks. The algorithm uses a prohibitive greedy iterative improvement strategy to explore the design space efficiently. A system-level floorplanner is used to evaluate the iterative design improvements and provide feedback on the effects of the topology on wire length. The algorithm is integrated within a NoC synthesis framework with characterized NoC power and area models to allow accurate exploration for a NoC router library. We apply the topology generation algorithm to several test cases including real-world and synthetic communication graphs with both regular and irregular traffic patterns, and varying core sizes. Since the method is iterative, it is possible to start with a known design to search for improvements. Experimental results show that many different applications benefit from a mix of ;on chip networks; and ;point-to-point networks;. With such a hybrid network, we achieve approximately 25% lower energy consumption (with a maximum of 37%) than a state of the art min-cut partition based topology generator for a variety of benchmarks. In addition, the average hop count is reduced by 0.75 hops, which would significantly reduce the network latency.

The Network-on-Chip (NoC) plays an important role in high-speed and efficient communication in System-on-Chip architectures. However, the NoC topology can be extracted through reverse engineering attacks with the goal of making illegal copies or unauthorized access to interconnect structure and system parameters, including routing protocols and data traffic patterns, thereby posing a threat to the security of the entire system. Simultaneously, the demand for energy efficiency has resulted in the extensive use of power-gating techniques that selectively shut down specific components in the NoC when they are not used to reduce power consumption significantly. This paper introduces TOP, a scalable obfuscation method that can be integrated into power-gating controllers, which aims to fortify the NoC against reverse engineering attacks while providing near-zero additional latency during operation. TOP operates using security keys to assume control of network components and reconfigure its structure and routing paths, utilizing existing units designed for use by power-gating controllers. The mechanism incorporates two distinct obfuscation approaches for complete protection. The centralized approach combines power-gating and structure obfuscation, ensuring efficiency and scalability to corrupt the function and traffic pattern of the network. The distributed approach specifically addresses timing-based attacks by introducing timing violations and triggering malfunctions upon applying wrong key. The scalability, energy efficiency, and minimal latency overhead of TOP, as evidenced by the average power, latency, and PDP overhead results across seven PARSEC programs in five different security levels (1.7-4.3%, 6-14.8%, and 7.8-19.7%, respectively), make it a suitable solution for safety-critical, high-performance, and resource-limited designs.

In this paper. The effect of intradie process variations oy the delay of tapered buffers designed in static CMOS logic style is analyzed in depth. An analytical delay model accounting for the dependency of variations on transistor sizing, load and input capacitance requirement is derived for the single stage. Then, this model is extended to the case of N-stage tapered buffers. The closed-form delay expressions includin. The contribution of intradie variations permit to gain an insight int. The impact of process variations oy the performance of tapered buffers. Monte Carlo simulations on a 90-nm technology including layout parasitica are performed to validat. The analysis. Results are shown to agree well wit. The expressions derived, thereby confirmin. The validity oy the underlying assumptions, as well at the suitability oy the proposed models for design purposes. © 2009 IEEE.

Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. In this work we present a design tool, SunFloor 3D, to synthesize application-specific 3D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components on to the 3D layers and performs a placement of them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3D and 2D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3D NoC when compared to the corresponding 2D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.

Fast and efficient processor allocation algorithm for torus-based chip multiprocessors

International audience

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the application traffic characteristics. The crossbar matrix and the arbiters of each switch in the NoC design are customized to support the traffic flows utilizing that switch. This application- specific switch customization is integrated with an existing design flow, which automates NoC topology synthesis, mapping, RTL code and physical layout generation. Several experimental studies on NoC benchmark designs are carried out, which show that the proposed switch customization technique leads to large reduction in the NoC switch area (28% on average) and power consumption (21% on average). Moreover, the critical paths of the switches reduce significantly, thereby leading to a significant speed-up of the NoC design.

Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL) in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

Building complex interconnect networks in a bottom-up way, for example by using self-assembling techniques, represents an ultimate challenge for building large-scale emerging computing devices. Due do the general lack of precise control over many self-assembling techniques, such interconnects are expected to be largely unstructured. In this paper we introduce two simple wire growth models for non-classical self-assembled network topologies. The models generate different unstructured and physically plausible network topologies. We then investigate the design trade-offs of such interconnect networks within a network-on-chip (NoC) simulation framework. In particular, we analyze the network's wiring cost and the communication properties by varying the framework's parameters. Our primary goal is to (1) investigate and understand the characteristics of such self-assembled networks and (2) to ultimately use these insights to tune experimental self-assembly process parameters. The quantitative simulation results show that unstructured NoC topologies obtained by the growth models show specific wire-length distributions that are beneficial for the communication and minimize the wiring cost. To support this result, we have also used an evolutionary optimization framework for the evolution of NoC topologies under given cost and communication requirements. Our results and the evaluation framework have implications for the design of interconnect architectures.