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  • https://doi.org/10.1109/jestpe.2026.3673748Copy DOI Icon

High Time Resolution DPWMs based on the Rolling Subtraction Algorithm

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Abstract

High time resolution is essential in digital DC-DC converters, but it is limited by physical implementation and resource consumption for basic delay unit-based digital pulse width modulations (DPWMs). This paper proposes a novel DPWM architecture with high time resolution based on the idea of rolling subtraction. In this architecture, the time resolution is not equal to the basic delay as usual, but equal to the delay difference. Therefore, a high time resolution can be achieved by subtracting two delays with a small difference. Besides, two DPWMs with more functions, which are independent deadtime adjustment and switching frequency adjustment, are implemented. This paper uses an Artix 7 field programmable gate array to implement the proposed DPWMs. The test results indicate that these DPWMs realize a high time resolution of 13ps, a high bit width of 16~24, and a high linearity larger than 0.99954 at low resource cost.

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