Holistic methods for protecting and testing embedded devices

Medical device reliability is the ability of medical devices to endure functioning and is indispensable to ensure service delivery to patients. Preferred Reporting Items for Systematic Review and Meta-Analyses (PRISMA) technique was employed in May 2021 to evaluate existing reporting guidelines on medical device reliability. The systematic searching is conducted in eight different databases, including Web of Science, Science Direct, Scopus, IEEE Explorer, Emerald, MEDLINE Complete, Dimensions, and Springer Link, with 36 articles shortlisted from the year 2010 to May 2021. This study aims to epitomize existing literature on medical device reliability, scrutinize existing literature outcomes, investigate parameters affecting medical device reliability, and determine the scientific research gaps. The result of the systematic review listed three main topics on medical device reliability: risk management, performance prediction using Artificial Intelligence or machine learning, and management system. The medical device reliability assessment challenges are inadequate maintenance cost data, determining significant input parameter selection, difficulties accessing healthcare facilities, and limited age in service. Medical device systems are interconnected and interoperating, which increases complexity in assessing their reliability. To the best of our knowledge, although machine learning has become popular in predicting medical device performance, the existing models are only applicable to selected devices such as infant incubators, syringe pumps, and defibrillators. Despite the importance of medical device reliability assessment, there is no explicit protocol and predictive model to anticipate the situation. The problem worsens with the unavailability of a comprehensive assessment strategy for critical medical devices. Therefore, this study reviews the current state of critical device reliability in healthcare facilities. The present knowledge can be improved by adding new scientific data emphasis on critical medical devices used in healthcare services.

With the development of information technology, integrated circuits (IC) and system which target high performance and low power consumption have widely penetrated to all the aspects of national economy, national defense construction and people’s life. With the continuous increase in IC integration density, the power consumption is becoming the limiting factor. It turns out that the driving force of the future IC and system development is the reduction of the power consumption and improvement of the performance/power ratio. The Moore’s Law is inherently the law for the technology and economic development, and has served as the guideline of the IC development for half a century. However, with the scaling down of IC feature size and the corresponding increased integration density, it is progressively approaching the physical limitation. Moore’s Law will gradually complete its historic mission and it will be replaced by a law of reducing the power consumption while ensuring the performance requirements for IC, SoC and SiP performance, law of improving the performance/power ratio. This paper will discuss the related research topics on Green micro/nanoelectronics, including low-power design, novel low-power devices, manufacturing processes for low power applications and related micro/nano electromechanical systems.

To solve the problems of insufficient acceleration capability and high power consumption of the existing embedded terminal target detection, a multi-strategy optimization hardware accelerator based on the YOLOv2 model is designed by taking advantage of the high concurrency characteristics of the CPU+FPGA structure. The accelerator improves its parallelism and real-time performance while reducing power consumption and resource consumption through floating-point quantization, adder optimization, and various HLS optimization strategies. Tested on Xilinx’s PYNQ-Z2 platform, the overall computing power of the accelerator reaches 27.1GOP/s, the average detection accuracy is 80.6%, and the overall power consumption is 2.609W. Compared with CPU and GPU, the obtained accuracy only loses 2%, but the power consumption is greatly reduced. It has strong practical significance in edge target detection that requires high real-time performance and low power consumption.

In recent years, electrocardiogram measuring instruments have been developing towards miniaturization, which has also promoted the development of miniaturization of circuits and low power consumption. FIR filters are suitable for filtering out noise and revealing the obvious characteristic waveforms in an electrocardiogram, but they have high power consumption. Therefore, under the premise of maintaining stable performance and the advantages of low power consumption, this paper proposed a new architecture named the compass form FIR filter. When the high order number M = 256, the power consumption of the linear phase form was 28.2112 mW, while the power consumption of the compass form FIR was 24.0749 mW. The power consumption of the compass FIR was lower than that of the linear phase form FIR, with a difference of 4.1363 mW. Therefore, the compass form FIR filter designed in this paper had the advantages of low power consumption and high filtering performance under set conditions and high order specifications.

A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.

With the popularity of portable electronic devices, the demand for 12-bit low-power analog-to-digital converter (ADC) chips continues to grow. Considering that these devices typically rely on battery power, high precision and stability are crucial. In order to improve the voltage resistance of ADC chips under high voltage, an innovative bootstrap sampling switch design is proposed, which utilizes the capacitance characteristics of NMOS and PMOS transistors to enhance the voltage resistance of the chip. At the same time, considering factors such as power fluctuations, time domain and voltage interleaving, a two-stage hybrid architecture based on successive approximation registers (SARs) and time to digital converters (TDCs) was studied and designed to optimize the balance between low power consumption and high voltage resistance performance. The results showed that the power consumption of the chip design was only 9.5 mW. The voltage compensation measures significantly reduced the error value from 7.01% to 1.97%, optimizing 5.04%. In summary, this design not only improves the accuracy and speed of ADC chips, but also successfully controls the exponential growth of power consumption, which has strong practical value. The proposed solution by the research institute has broad potential in multiple application fields, especially suitable for situations with high requirements for power consumption and stability, such as medical imaging and aerospace. This design provides new ideas and directions for the development of high-performance and low-power ADC chips in the future.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

We have proposed a memory based recursive FFT design which has much less gate counts, lower power consumption and higher speed. The proposed architecture has three main advantages (1) fewer butterfly iteration to reduce power consumption, (2) pipeline of radix-22 butterfly to speed up clock frequency, (3) even distribution of memory access to make utilization efficiency in SRAM ports. In summary, the speed performance of our design easily satisfies most application requirements of Fixed 802.16d and Mobile 802.16e WiMAX, which uses OFDMA modulated wireless communication system. Our design also occupies lesser area, hence lower cost and power consumption.

Reference architectures provide template solutions for particular domains and can therefore be considered as standards. This study investigates whether diversity in enterprise reference architectures is likely to continue or if one reference architecture will gain dominance in the market. More specifically, we examine factors that lead to market dominance. We use the literature on standards battles, the Technology Acceptance Model (TAM), and the Technology-Organization-Environment (TOE) framework to analyse factors for dominance. In this field, network effects apply and provide a force towards the dominance of a single architecture. However, factors contributing to multiple standards are more relevant, as well as those from TAM and TOE, since reference architectures differ slightly in their added value for various categories of stakeholders. Empirical data from 19 expert interviews provide further insights into the factors that influence the dominance of an enterprise reference architecture. Our results show that it is important that the content and value of reference architectures are straightforward and understandable, not only for architects but for all stakeholders. We extend current standards battles literature by applying it to a new area and combining it with TAM and TOE. We provide an innovative and extensive list of factors that influence the dominance of one standard and the continued coexistence of multiple standards and relate these to phases of technology development. This list can form a framework for future standards battle research. From the practical perspective, the annex may help parties involved in standard battles to position themselves in the technology development phase, better predict the outcome of the battle, and enhance the possibility to influence that outcome. More specifically, our paper will help adopters of enterprise reference architectures to make better-informed choices. Suppliers of reference architectures can use the findings to stimulate market adoption of their model.

Next-generation memories with high storage capacity, high performance, and low power consumption are being researched due to the ever-growing demand for artificial intelligence and high-definition applications. Among such future memories, a multi-level cell (MLC) spin-transfer magnetic torque random access memory (STT-MRAM) attracts considerable attention as an alternative to static or dynamic random access memories. An MCL STT-MRAM has the advantages of capacity and non-volatility, but the disadvantages of performance, power consumption, and endurance resulting from complicated resistance state transition and detection processes. In particular, such issues are exacerbated in the latest smart image applications employing block-based processing algorithms. In this paper, we propose a memory subsystem that mitigates the MLC STT-MRAM disadvantages in smart image applications. Our main idea is threefold: MLC-aware image buffer composing, block-aware pixel-to-memory mapping, and prediction-aware image-to-buffer allocating techniques that all make multi-step resistance state transition and detection processes less required. Experimental results show that the proposed memory subsystem achieves 24.5% shorter application execution time, and 96.4% lower memory power consumption than the conventional memory subsystems for industrial smart image applications. In addition, our memory subsystem increases the lifetime of MLC STT-MRAMs via 93.8% fewer multi-step resistance state transition processes.

This paper investigates the electromagnetic compatibility of 45 critical care medical devices (infusion pumps, defibrillators, monitors, lung ventilators, anesthesia machines and external pacemakers) with various types of wireless local area network (WLAN, IEEE 802.11 b/g, 2.45 GHz, 100 mW) adapters. Interference is evaluated by performing ad-hoc tests according to the ANSI C63.18 recommended practice. The behavior of the devices during the tests was monitored using patient simulators/device testers specific for each device class. Electromagnetic interference cases were observed in three of 45 devices at a maximum distance of 5 cm. In two cases the interference caused malfunctions that may have clinical consequences for the patient. The authors' findings show that the use of these wireless local area network adapters can be considered reasonably safe, although interference may occur if they are operated at very close distance (<10 cm) to the medical devices.

Decorative plating processes for common plastic resins: Resin selection as well as plastic part design is critical to matching the right finishing method with the intended application

This paper describes development of a novel mid-infrared light emitting diode (LED) and photodiode (PD) light source/detector combination and use within a non-dispersive infrared (NDIR) carbon dioxide gas sensor. The LED/PD based NDIR sensor provides fast stabilisation time (time required to turn on the sensor from cold, warm up, take and report a measurement, and power down again ≈1 second), longevity (>15 years), low power consumption and low cost. Described performance is compatible with “fit and forget” wireless deployed sensors in applications such as indoor air quality monitoring/control & energy conservation in buildings, transport systems, horticultural greenhouses and portable deployment for safety, industrial and medical applications. Fast stabilisation time, low intrinsic power consumption and cycled operation offer typical energy consumption per measurement of mJ's, providing extended operation using battery and/or energy harvesting strategies (measurement interval of ≈ 2 minutes provides >10 years operation from one AA battery). Specific performance data is provided in relation to measurement accuracy and noise, temperature performance, cross sensitivity, measurement range (two pathlength variants are described covering ambient through to 100% gas concentration), comparison with NDIR utilizing thermal source/pyroelectric light source/detector combination and compatibility with energy harvesting. Semiconductor based LED/PD processing together with injection moulded reflective optics and simple assembly provide a route to low cost high volume manufacturing.

In the article the possibility of using a smartphone with an integrated set of necessary technical means (several video cameras, accelerometers, gyroscope, magnetometer, GPS sensor, GSM and Wi-Fi wireless communication) for implementing the technology of video recording of vehicle speed is investigated and established. The main algorithmic and software components of a smartphone are proposed, which allow to identify and to accompany a vehicle, as well as to determine its speed. Installation and initial setup of the device is simple. It is only necessary to measure and enter in the device height of its arrangement. In the article the possibility of using a smartphone with an integrated set of necessary technical means for implementing the technology of video recording of vehicle speed is investigated and established. The smartphone has a low cost and power consumption, the ability to operate in the required temperature range, as well as a set of physically built-in necessary technical means: several video cameras, accelerometers, gyroscope, magnetometer, GPS sensor, GSM and Wi-Fi wireless communication. Due to its low power consumption, it can also run on solar panels during the day when no other power source is available. The cost of a smartphone with very good characteristics does not exceed 10,000 UAH. The paper proposes the main components of the algorithmic support of the device. The use of the Lucas-Kanade method for the implementation of tracking and the calculation in the interpixel space of the coordinates of the points of the vehicle's trajectory will improve the accuracy of measurements of the traveled distance and the vehicle's speed on short sections of the trajectory. The proposed algorithm for calculating the vehicle speed requires entering only one parameter - the height of the device. Therefore, installation and initial setup of the device is simple. It is enough to measure and enter this parameter into the device. Large-scale introduction of a device for measuring vehicle speed, built on the basis of a smartphone, is possible due to relatively small investments in the development of its mechanical part, algorithmic and software.

IEEE 802.15.4 standard defines both media access control (MAC) and physical (PHY) layer protocols for low power consumption, low peak data rate, and low cost applications. Nowadays the most important feature of IEEE 802.15.4 is maximizing battery life. This paper is focusing how to achieve low average power consumption through assuming that the amount of data transmitted is short and that it is transmitted infrequently so as to keep a low duty cycle. The outcomes demonstrate that the phase shift estimation of Offset quadrature phase-shift keying (OQPSK) modulation has no impact on bit error rate (BER) if it is identical in the transmitter as same as in the receiver.