Hot carrier effects in MOS transistors

0C (43K) in the polar shadows), makes operation of the electronics sub-systems on the surface of the Moon exceptionally difficult, but is nonetheless required for the envisioned complex suite of electronics systems used in sensing, actuation, and control of robotic systems. Such applications are typically fairly low frequency in nature (e.g., < 100 MHz), hence not requiring the most aggressively scaled CMOS technology; however, a full suite of mixed-signal circuit building blocks, and reliable operation of those circuits across extremely large variations in temperature (e.g., +120 to -230C) is needed. Adequate device reliability must clearly be achieved to accomplish this task. CMOS device degradation due to hot carriers effect (HCE) is known to be considerably worse at low temperatures [2]. Device lifetime data at cryogenic temperatures, and a solid understanding of the corresponding degradation mechanisms, are thus critical in this context of space electronics, and are addressed in this work. The Si CMOS devices investigated here are from an advanced 0.5µm SiGe BiCMOS technology, with a fixed channel width of 10.0 µm, and effective gate lengths ranging from 0.35 µm (minimum geometry), to 5.0 µm. The devices were characterized on a custom cryogenic probe system from 300K down to 43 K (-230 0 C). For brevity we will focus on the nFET data, since it represents the worst case in this technology. Fig. 1 and 2 shows typical I-V characteristics for the CMOS devices at different temperatures. The current drive capability increases significantly for the same bias conditions, as the temperature decreases. The nFET lifetime was inferred using stress-induced changes to the ID-VG characteristics. The lifetime τ is defined here as the inferred stress time for which a certain parameter of the ID-VG characteristics has shifted by a predefined amount (e.g., 10% degradation of gm). A typical lifetime assessment analysis using the ID-VG characteristics for a 1.0 µm nFET are shown in Fig. 3 and Fig. 4. The slope of 0.6 for the linear fitting in Fig. 4 suggests that interface state generation is responsible for the observed device degradation at the maximum substrate current (VG ≈ ½ VD); while that of 0.3 for the maximum gate current bias condition (VG = VD) suggests that oxide trapped charge dominates [3]. For the nFETs operating at 300K, the worst case bias condition for hot carrier degradation is known to be under maximum substrate current bias. There has been speculation that the worst case bias conditions for hot carrier degradation can, however, be a function of temperature [4]. It can be verified from Fig. 4 that for this technology, maximum substrate current is indeed the worst bias condition, at least down to 82K, and hence was the condition used here for device lifetime evaluation. The substrate current is comprised of the generated hot carriers, and is thus a good monitoring parameter for HCE in practical measurements. Fig. 5 and Fig. 6 show the effects of temperature and gate length on substrate current, respectively. It can be seen from Fig. 5 that the maximum substrate current under the same bias condition increases by 3x as temperature decreases from 300K to 43K; while Fig. 6 suggests that the maximum substrate current increases by more than 10x as L shrinks from 1.0 µm to 0.35 µm, and becomes negligible as L increases to 5.0 µm. This suggests that HCE is impacted more by device geometry than by the temperature. Fig. 7 shows the inferred lifetime at different drain bias’ at different temperatures. As seen in Fig. 7, τ decreases by ~10x as the temperature is reduced from 300K to 82K. Furthermore, τ differs by more than 100x between the 1.0 µm and 0.35/5 µm transistors, and hence the longer-channel devices are preferred for cryogenic applications of this technology Assuming fast interface trap generation dominates the HCE degradation, plotting τID versus ISUB/ID on a log-log scale should yield a straight line behavior [5]. The critical electron energy for generating an interface trap is calculated to be 3.9 eV from the slop of the line. Both the slope and the critical energy from Fig. 8 correlate well with literature data (2.9 and 3.7 eV in [5]), suggesting that interface state generation is the dominant limiting reliability factor at low temperatures.

Hot carrier degradation of InGaZnO thin film transistors under light illumination at the elevated temperature

In this paper, a new approach is presented for esti- mating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time- Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user- specified deterministic input waveform are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general- purpose simulator and tested on a number of typical examples and benchmarks.

In this work, performance degradation of 65 nm N-channel metal-oxide-semiconductor field effect transistors (NMOSFETs) with enclosed gate and two-edged gate layouts under hot carrier stress and constant voltage stress is investigated. Compared with the cold carrier, the hot carrier effect (HCE) causes more serious degradation in threshold voltage and transconductance. It is shown that cold carrier contribution is reversible, while HCE damage is permanent, it cannot be reversed by application of the annealing bias. Meanwhile, an enclosed gate NMOSFET is proved to have higher resistance to HCE than two-edged gate NMOSFET fabricated in the same 65 nm complementary metal-oxide-semiconductor (CMOS) technology according to the results of experiments. That is, the enclosed gate NMOSFET not only provides total-dose radiation tolerance but also improves the hot carrier reliability of advanced CMOS circuits. The contributions of the two types of carriers to the degradation of transistor performance are analysed. The physical mechanism of HCE reliability of different geometry MOSFETs is studied.

A study of hot carrier reliability of n-channel SiON and HfSiON MOSFETs with poly-Si gate is proposed. During hot carrier stress, both interface state and bulk defect generation were observed. A comparison for different stress conditions, i.e., maximum substrate current and maximum electron injection, is provided. HfSiON MOSFETs show longer lifetime, if defined in terms of device performance, than MOSFETs with SiON with similar equivalent oxide thickness. Finally, we show that hot carrier degradation strongly reduces gate stack lifetime with respect to the Fowler-Nordheim stress commonly used to evaluate the time dependant dielectric breakdown.

In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of an LDD MOSFET after hot carrier stress. The spatial distribution of interface states is calculated with a combined Monte Carlo and breaking silicon-hydrogen bond model. A 0.6 /spl mu/m LDD MOSFET was characterized to compare the simulation. A reduction of the substrate current at V/sub gspl cong/0.5 V/sub d/ in a stressed device was observed from both measurement and simulation. Our study reveals that the reduction is attributed to a distance between the maximum channel electric field and the generated interface states.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this work experimental data of thick MOS gate oxides (25 nm) of a state of the art 90 nm technology are assessed for degradation from plasma induced charging (PID). It is demonstrated that the type of stress measurement and the data analysis approach are crucial for the interpretation of the experimental data and for lifetime estimation. Two PID stress measurements are compared: hot carrier stress and Fowler-Nordheim stress. Different data analysis concepts illustrate that the usual technique can give misleading analysis results, just calculating the drift of MOS transistor parameters. It is shown that the type of PID protection for MOS transistor test structures plays a significant role in the misinterpretation of MOS device data.

Crystallographic-orientation-dependent GIDL current in Tri-gate MOSFETs under hot carrier stress

The creation of defects by hot-carrier effect in submicrometer (0.85- mu m) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V/sub d//8 to V/sub d/) by hot-hole and/or hot-electron injections, and their generation rates (10/sup -9/ and 10/sup -2/ for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I/sub d/-V/sub g/ degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I/sub d/-V/sub g/ degradation. >

Hot carrier effects in n-MOSFETs with SiO 2/HfO 2/HfSiO gate stack and TaN metal gate

An investigation of hot carrier effects in submicron CMOS integrated circuits

Determination of interface state density in MOSFETs using the spatial profiling charge pumping technique

The charge pumping technique is used to characterise interface states in MOSFETs created by hot-electron injection. Donor states near the middle of the bandgap are identified. Two independent methods to determine the location of these states are presented.

In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> is less than half of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> .