HPP: A High Performance PRAM

The next generation VLSI circuits will be designed with millions of densely packed interconnect segments on a single chip. Inductive effects between these segments begin to dominate signal delay as the clock frequency is increased. Modern parasitic extraction tools to estimate the onchip inductive effects with high accuracy have had limited impact due to large computational and storage requirements. This work describes a parallel software package for inductance extraction called ParIS, which is capable of analyzing interconnect configurations involving several conductors within reasonable time. The main component of the software is a novel preconditioned iterative method that is used to solve a dense complex linear system of equations. The linear system represents the inductive coupling between filaments that are used to discretize the conductors. A variant of the fast multipole method is used to compute dense matrix-vector products with the coefficient matrix. ParIS uses a two-tier parallel formulation that allows mixed mode parallelization using both MPIand OpenMP. An MPI process is associated with each conductor. The computation within a conductor is parallelized using OpenMP. The parallel efficiency and scalability of the software is demonstrated through experiments on the IBM p690 and Intel and AMD Linux clusters. These experiments highlight the portability and efficiency of the software on multiprocessors with shared, distributed, and distributed-shared memory architectures.

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption and low cost requirements, embedded systems are often customized to a single application, or a very small set of applications. In addition, time-to-market requirements and the increasing complexity of embedded systems drives the need for fully or partially automated design tools and also to the extensive use of caches and cache hierarchies. The introduction of multi-processor-based embedded platforms has accelerated this trend; as the design space for embedded systems has grown, designers have become unclear as to whether automatic processor customization tools can cope with this increased complexity. The recent introduction of new techniques addressing the automatic customization, such as Architecturally Visible Storage (AVS) memory-enhanced Instruction Set Extension (ISE) identification algorithms, has also created new challenges. AVS memories are distinct from the cache hierarchy and rely on Direct Memory Access (DMA) transfers to communicate with main memory. In an embedded system containing hardware-managed caches, these extra AVS memories, in combination with their corresponding DMA transfers, cause coherence and consistence problems. Although the problems of coherence and consistence are well known in multi-processor systems, conventional solutions may be expensive in terms of area and power consumption, rendering them unacceptable for use in embedded systems. This thesis presents two low cost coherence mechanisms that solve these two problems. The first mechanism addresses embedded systems that already contain a hardware coherence protocol, like many high-end embedded multi-processor systems. Traditionally, the DMA transactions are transparent to the hardware coherence protocol. By ensuring visibility of these DMA transactions to the hardware coherence protocol, coherence can be guaranteed between AVS memories and data cache(s). As a result, minor changes to the DMA engine are required. Moreover, by forcing the processor pipeline to stall if a DMA transfer is active, memory consistence can be guaranteed. This mechanism provides significant speedup when compared to the execution of a non-ISE-enhanced system; however, due to the increase in bus traffic, this speedup comes at the expense of an increase in energy consumption. Coherent and Speculative DMA are both implementations of this mechanism. Single-processor systems do not contain hardware coherence protocols, and would therefore benefit from a lower-cost solution to the coherence and consistence problems than a hardware coherence protocol. By tightly coupling the AVS memories to the hardware cache, coherence and consistence for the complete system can be guaranteed. This coupling requires insignificant changes to the hardware cache's hit detection circuitry and state machine without influencing its critical path, thus it is inherently inexpensive. This mechanism provides significant speedups and reduces the energy consumed if compared to the execution on non-ISE-enhanced systems. Furthermore, the tight coupling enables direct communication between the AVS memories and the data cache, making this mechanism independent from the processor-to-memory distance. Virtual Ways and Way Stealing are both implementations of this mechanism. Besides enforcing coherence and consistence, the ability to integrate the architectural changes into an automated design flow is important. This thesis shows the influence of Coherent DMA, Speculative DMA, Virtual Ways, and Way Stealing on the ISE-identification algorithm. It shows the architectural requirements and the cost for enforcing coherence and consistence that need to be taken into account when applying these mechanisms in an automated flow without formulating new algorithms.

The trend of using heterogeneous computing and HW/SW-Codesign approaches allows increasing performance significantly while reducing power consumption. One of the main challenges when combining multiple processing devices is the communication, as an inefficient communication configu-ration can pose a bottleneck to the overall system performance. To address this problem, we present a methodology that assists the designer in making good design decisions for systems using shared DDR memory for communication. Our methodology analyzes a software implementation of the application and subsequently predicts the memory accesses of a functionallyequivalent hardware implementation of the selected function. We furthermore propose an IP core that can perform these predicted memory accesses to estimate the achievable memory bandwidth between a functionally equivalent hardware implementation and shared memory. The resulting achievable memory bandwidth estimations differ by less than 2% from the actual achievable memory bandwidth of a functionally equivalent hardware implementation, demonstrating the feasibility of the presented methodology.

We describe a powerful framework for designing efficient batch algorithms for certain large-scale dynamic problems that must be solved using external memory. The class of problems we consider, which we call colorable eztemaldecomposable problems, include rectangle intersection, orthogonal line segment intersection, range searching, and point location. We are particularly interested in these problems in two and higher dimensions. They have numerous applications in geographic information systems (GIS), spatial databases, and VLSI and CAD design. We present simplied algorithms for problems previously solved by more complicated approaches (such as rectangle intersection), and we present efficient algorithms for problems not previously solved in an efficient way (such as point location and higherdimensional versions of range searching and rectangle intersection). communication is the bottleneck in many large-scale applications such as those arising in VLSI and CAD design, spatial databases, and geographic information systems (GIS). In this paper we consider I/O-efficient algorithms for batched searching problems. We consider both batched static and batched dynamic problems, and use the correspondence which often exists between a ddimensional static problem and a (dl)-dimensional dynamic problem to obtain a number of new d-dimensional algorithms. We give experimental results concerning the running time for our approach applied to the red-blue rectangle intersection problem, which is a key component of the extremely important database operation spatial join. Our algorithm scales well with the problem size, and for large problems sizes it greatly outperforms the well-known sweepline approach. One prominent example of the problems we consider is the rectangle intersection problem, which is a key component in VLSI design rule checking [31] and in the extremely important database operation spatial join [34]. We illustrate the practical significance of our algorithms by comparing the empirical performance of our algorithm for this problem with the well-known sweepline algorithm developed for internal memory. 1.1 Problem definition and memory model

Emerging cache-coherent non-uniform memory access (cc-NUMA) architectures provide cache coherence across hundreds of cores. These architectures change how applications perform: while local memory accesses can be fast, remote memory accesses suffer from high access times and increased interconnect contention. Because of these costs, performance of legacy code on NUMA systems is often worse than their uniform memory counterparts despite the potential for increased parallelism.We explore these effects on prior implementations of concurrent stacks and propose the first NUMA-friendly stack design that improves data locality and minimizes interconnect contention. We achieve this by using a dedicated server thread that performs all operations requested by the client threads. Data is kept in the cache local to the server thread thereby restricting cache-to-cache traffic to messages exchanged between the clients and the server. In addition, we match reciprocal operations (pushes and pops) by using the rendezvous elimination algorithm before sending requests to the server. This has the dual effect of avoiding unnecessary interconnect traffic and reducing the number of operations that change the data structure. The result of combining elimination and delegation is a scalable and highly parallel stack that outperforms all previous stack implementations on NUMA systems.

The off-chip memory bandwidth is often a critical part of a video processing system. Traditional cache usually behaves poor since some video algorithms such as motion compensation tend to access memory in an inefficient way. A memory bandwidth efficient architecture for video decoder is proposed in this paper. Two bandwidth optimization strategies are proposed to minimize the memory bandwidth. Experimental results show that two strategies succeed in reducing external memory bandwidth of motion compensation by 30% and the data arrangements strategy can solve the latency problem better than previous solutions. compensation tend to access memory in an inefficient way. A memory bandwidth efficient architecture for video decoder is proposed in this paper. Two bandwidth optimization strategies are proposed to minimize the memory bandwidth. Experimental results show that two strategies succeed in reducing external memory bandwidth of motion compensation by 30% and the data arrangements strategy can solve the latency problem better than previous solutions.

ILP processors can execute a large number of instructions at the same time. Thus it becomes more and more difficult to support traps efficiently. On the other hand a current trend in architecture is to support various memory functions in software rather than hardware, usually by trapping the execution processor on a cache miss, TLB miss or a failed access to a local or remote memory. These late memory traps block the faulting instruction at the top of the active list, backing up the pipeline. Moreover the support for late memory traps may affect the performance of non-faulting memory instructions as well.In this paper we analyze the overhead caused by late memory traps in ILP processors and define several measures for this overhead. In order to tolerate late memory traps, we propose hardware prefetching of exception conditions and a tagged Store buffer to implement deferred traps on Stores. We show that, with these hardware optimizations, the overhead added by the lateness of traps is significantly reduced relative to the overhead of early traps. Because of caching effects the frequency of late memory traps usually decreases as they are taken deeper in the memory hierarchy and their overall impact on the execution time becomes negligible.

The ray tracing algorithmis well-known for its ability to generate high-quality images and its flexibility to support advanced rendering and lighting effects. Interactive ray tracing has been shown to work well on clusters of PCs and supercomputers but direct hardware support for ray tracing has been difficult to implement.In this paper, we present a new, scalable, modular, and highly efficient hardware architecture for real-time ray tracing. It achieves high performance with extremely low memory bandwidth requirements by efficiently tracing bundles of rays. The architecture is easily configurable to support a variety of workloads. For OpenGL-like scenes our architecture offers performance comparable to state-of-the-artrasterization chips. In addition, it supports all the usual ray tracing features including exact shadows, reflections, and refraction and is capable of efficiently handling complex scenes with millions of triangles. The architecture and its performance in different configurations is analyzed based on cycle-accurate simulations.

We propose a new circuit analysis method, namely Semi-Implicit Linear-Centric Analysis (SILCA), for efficient SPICE-accurate transient simulation of deep-submicron VLSI circuits with strong parasitic coupling effects introduced by interconnect lines, common substrate, power/ground networks, etc. SILCA is based on two linear-centric techniques. First, a new semi-implicit iterative numerical integration scheme is developed, which applies dynamic time step control accounting for stiff systems and meanwhile keeps constant equivalent conductance for capacitor/inductor companion models. Its convergence and stability properties are characterized. Second, to achieve constant linearized conductance for nonlinear devices during nonlinear iteration process, a successive variable chord method is introduced as an alternative of the Newton-Raphson method and the rank-one update technique is implemented for fast LU factorization. With these techniques, SILCA reduces the number and cost of required LU factorizations dramatically. Experimental results on substrate and power/ground networks have demonstrated that SILCA yields SPICE-like accuracy with an over 80X reduction in LU factorization cost, and an about 20X overall CPU time speedup over SPICE3 for circuits with tens of thousands elements, and the efficiency increases further with the size of a circuit.

The field of application for distributed algorithms is growing with the ongoing demand for new network applications. Wherever a global goal must be achieved by a number of peers, a distributed algorithm consisting of local computations and communication protocols must be developed. In asynchronous environments the design of a distributed algorithm must respect the fact that processes may vary in speed and that messages might be delayed for an arbitrarily long time. Moreover, it is often required that the algorithm still works in the presence of crash failures, i.e., in scenarios, where some processes stop working at some time. The complex nature of concurrent executions in distributed systems often hinder the application of common methods for modeling and verification. Although many different formal approaches for modeling fault tolerant distributed algorithms, like e.g. I/O automata and process calculi have been proposed, many works in the field of distributed systems use informal pseudo-code representations to introduce new algorithms. On most cases this leads to informal and crude arguments for correctness, which usually become incomprehensible if all race conditions must be taken into account. This work proposes new formal strategies to model and verify distributed algorithms, whereas we focus on two main goals. Firstly, we introduce a means to satisfy a designer’s demands by using methods that are easy to understand and to work with and which are very similar to common applied methods as e.g. TLA and Abstract State Machines. Secondly, our strategies are suitable for the formal use in a theorem proving environment. This enables mechanical verification of our algorithms and therefore, we are able to produce machinechecked proofs for correctness. Our model adopts abstractions from the work of Fuzzati, which examines two similar distributed algorithms in a logical framework. We lifted these abstractions to a more general level to make them suitable and reusable for as many distributed algorithms as possible. Furthermore, we present a new method to place local computation steps in the respective global context. The advantage of our method is that, on the on hand, like with pseudo code, computations can be described as local steps, but, on the other hand, it is possible to formally reason over global system states. Our model for communication mechanisms comprises modules for different kinds of message passing, broadcasts, and shared memory access. We are convinced that our model can easily be extended to support almost all kinds of communication infrastructures that can formally be described. We show how properties that have to be verified can be expressed in terms of our model to enable formal reasoning. Furthermore, we present appropriate strategies to verify different classes of properties. For the theorem proving environment Isabelle/HOL we provide a library which incorporates all introduced abstractions and can, therefore, be reused and extended for further applications, new algorithms, and further verification projects. Finally, we present case studies for the verification of different distributed algorithms to demonstrate the applicability of our strategies. Four known algorithms are verified in our model using our framework for Isabelle/HOL. The algorithms vary in complexity, the used communication infrastructure, the failure model, and other constraints, so that many different modeling and verification aspects are exemplified.

Communication in a parallel system frequently involves moving data from the memory of one node to the memory of another; this is the standard communication model employed in message passing systems. Depending on the application, we observe a variety of patterns as part of communication steps, e.g., regular (i.e. blocks of data), strided, or irregular (indexed) memory accesses. The effective speed of these communication steps is determined by the network bandwidth and the memory bandwidth, and measurements on current parallel supercomputers indicate that the performance is limited by the memory bandwidth rather than the network bandwidth.Current systems provide a wealth of options to perform communication, and a compiler or user is faced with the difficulty of finding the communication operations that best use the available memory and network bandwidth. This paper provides a framework to evaluate different solutions for inter-node communication and presents the copy-transfer model; this model captures the contributions of the memory system to inter-node communication. We demonstrate the usefulness of this simple model by applying it to two commercial parallel systems, the Cray T3D and the Intel Paragon.In particular we identify two methods to transfer data between nodes in these two machines. In buffer-packing transfers, a contiguous block of data is transferred across the network. If the data are not stored contiguously, they are copied to (gathering) or from (scattering) buffers in local memory before and after the transfer. Chained transfers perform gathering, transfer and scattering in one step, reading the data elements with some non-sequential pattern and immediately transferring them on to the destination.Our model and measurements indicate that chaining of the gather, transfer, and scatter operations results in better performance than buffer packing for many important access patterns. Most standard message passing libraries (like MPI, PVM or NX) force the parallelizing compiler (or the programmer) to employ the buffer-packing communication operations. However, the addition of hardware support dedicated to communication (e.g., DMAs, line-transfer units) now gives the compiler a wider range of options.

There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T and asymmetric 9T SRAM cells and calculated various design parameters using simulation of mentioned circuits at 70 nm. Here, to find better parametric compression, different cell ratios were also considered. From the simulation results, it is found that using MTCMOS design techniques, leakage current is effectively suppressed but on account of delay penalty. The delay penalty can also be minimized by selecting properly sized inverter cell. Keywords: SRAM, stability, SNM, MTCMOS Cite this Article Nidhi Tiwari, Vaibhav Neema, Rangra Kamal J et al. Comparative Analysis of Different SRAM Cells Architecture at 70 nm. Journal of VLSI Design Tools & Technology. 2018; 8(2): 33–41p.

We describe the operational principles of a scalable hardware accelerator for volume rendering. The basic philosophy is to provide an atomic unit which already provides sophisticated volume graphics at interactive rendering speed. Realtime speed can then be achieved by operating multiple units in parallel. The basic unit consists of just four VLSI chips and the volume memory and thus meets the requirements of a small size and low costs. Nevertheless it provides arbitrary perspective projections (e.g., for walk-throughs), Phong shading, a freely moveable light source, depth-cueing and interactive, non-binary classification (semitransparent display) at a frame rate of about 2.5Hz for 2563 data sets.

A methodology for the redesign of sequential VLSI circuits to increase the circuit speed involves cascading the circuit over a plurality of time frames without the memory elements, identifying any long false paths in the cascaded circuit, reconfiguring the original circuit to eliminate the false paths while providing fanout to preserve functionality, and retiming the reconfigured circuit to reduce circuit delay.

Nuclear fusion, the merging of light nuclei into a heavier one, is an attractive future energy source. It is safe, produces no carbon-dioxide and its resources are practically unlimited. Currently, the most promising concept of nuclear fusion as a commercial energy source is the tokamak. In a tokamak, the hot plasma is confined by a torus shaped magnetic field. However, the plasma gradually diffuses outwards to the so-called scrapeoff layer and is guided to the divertor, the exhaust of a fusion device. In the divertor of ITER, a tokamak experiment under construction that has to demonstrate that fusion is a feasible energy source, an enormous heat flux density of around 10 MW m-2 and particle flux density of around 1024 m-2s-1 are expected. Pilot-PSI and Magnum-PSI, two linear plasma devices at DIFFER, are unique in producing the plasma conditions as expected in the ITER divertor in a well controlled and diagnosed set-up. Therefore, Pilot-PSI and Magnum-PSI are crucial for a successful divertor design for next generation tokamaks. Via computer simulations results of Pilot-PSI and Magnum-PSI can be translated to ITER. The wide ranges of time and length scales of the processes in the divertor make simulations very challenging. For simulation of neutral particles under ITER divertor conditions, a non-linear, kinetic Monte Carlo code is required. Hereto, Eunomia has been developed and coupled to the multi-fluid plasma code B2.5. Eunomia is a welldocumented, modular code with a modern fortran programming style, using objects and dynamic memory allocation. The challenging part of B2.5 simulations of Pilot-PSI and Magnum-PSI is to describe the low temperature, high density plasma beam in suitable boundary conditions. For Monte Carlo simulations of neutral species in a linear device the statistically most challenging region is the plasma region, in particular in front of the target. The aim for B2.5-Eunomia is to simulate both the geometries of linear devices and the scrape-off layer and divertor region of a tokamak and to improve understanding of the important physics in the ITER divertor conditions. Since for a new code validation is essential, Eunomia has been subjected to several test problems, such as Couette flow, to ensure correctness of neutral flow calculations. In addition, performance of several features of Eunomia has been tested, such as the parallel speedup and the algorithms reducing statistical noise. The importance of various collision processes has been studied. As expected, for Pilot-PSI conditions the neutral-neutral collisions and charge exchange collisions with a proton are of great importance. Although typically neglected, because of the small scattering angle, the elastic collisions between a proton and atomic and molecular hydrogen should be included at the relatively high pressure of several Pascals, created by the recycling plasma. The density distributions of excited hydrogen atoms and line-of-sight integrated Balmer emission profiles were calculated with a collisional-radiative model, using Eunomia results as input. Simulation of the vibrational states of the hydrogen molecule as separate species in Eunomia is crucial. The distribution of the molecules over the vibrational states strongly deviates from local thermal equilibrium, due to transport and dissociative processes. This has an impact on the shapes and intensities of the emission profiles. Comparison to spectroscopic measurements in Pilot-PSI showed reasonably good agreement in both the widths and amplitudes of the line integrated emission profiles of Balmer-a. However, the results are sensitive to uncertainties in the association probability of atoms at the vessel wall and the distribution of molecules, produced by this association process, over the vibrational states. B2.5-Eunomia has successfully been coupled and applied to the cylindrically symmetric geometry of Pilot-PSI. The vibrationally excited molecules efficiently recombine the plasma at the edge of the plasma beam, whereas atoms efficiently cool the plasma. Comparison of B2.5-Eunomia simulations to Thomson scattering measurements near the target of Pilot-PSI showed good agreement. B2.5-Eunomia could not reproduce the floating potential and the saturation current to the target quantitatively, however, the amount of biasing required to reach saturation of the total current to the target is reproduced. When the target in Pilot-PSI is floating, so when the total net current is zero, locally strong plasma currents run into and out of the target. B2.5-Eunomia results show current paths from the anode to the target, returning via the center of the plasma to the source. Furthermore, B2.5-Eunomia simulations show that saturation of the total current, as measured experimentally in Pilot-PSI for a biased target, is not a good indicator for obtaining the ion saturation current density over the whole target surface. Locally, at the center of the target, the ion saturation current is only reached when biasing the target 20 V more negative. Only when locally the ion saturation current density has been reached, the sheath potential will increase linearly with the bias potential. Further development of Eunomia, to improve the B2.5-Eunomia code package in the future, and additional benchmarking of B2.5-Eunomia have been discussed. The incorporation of the collisional-radiative model has been initiated. There remain no technical limitations to simulate other linear devices, as well as tokamak divertors, with B2.5-Eunomia.