HV PMOSFET Vth (threshold voltage) shift caused by HEIP after HTOL

An ultra-thin natural-source-based cellulose derivate is used in a bilayer gate dielectric for organic complementary inverters. Extraordinarily high small-signal gains up to 1600, a very sharp transition region (as low as 40 mV), a full rail-to-rail swing, a balanced noise margin of 92.5%, and “long-time” stability are shown, revealing that these inverters are highly suitable for complex circuit designs. For more than a decade now the research in organic electronics was driven by unique consumer markets demanding for electronic circuits on flexible substrates over large areas and ideally at low cost. Meanwhile, versatile macroelectronic applications with attractive form factors such as flexible displays,1-4 large-area sensor arrays,5-11 e-paper,12, 13 low-cost radio-frequency identification tags,14-18 and bendable microprocessors19 have been realized using organic thin-film transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last five years to design unipolar inverters using p-type-only OTFTs.18-23 Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates.19, 22, 23 In this context, it stands beyond doubt that the integration of both n-type and p-type transistors in complementary organic-based circuits12 is very advantageous due to a lower power dissipation, higher noise margin, better operational stability, and easier design of the circuit.24-27 To date, several major obstacles complicated the development of organic complementary circuits, which are as follows: i) the lack of n-channel OTFTs with a performance comparable to the p-channel OTFTs, ii) the challenge of device stability (difficulty in fabricating OTFTs with hysteresis-free characteristics), and iii) the difficulty in fabricating sufficiently thin gate dielectrics allowing for low supply voltages. Although many recently reported complementary organic inverters are impressive with respect to their low operation voltages (≤5 V),27-36 high static gains (>100 V/V),25, 28, 30, 32 and large noise margins (>80%),25, 35, 37, 38 only few of those can combine low-voltage operation with high gain and sufficient immunity against electrical noise.39 Moreover, there have been few investigations of the influence of hysteresis and threshold voltage shifts on the inverter characteristics, which typically gives rise to electrical instabilities and performance limitations of those devices.32, 39 The inverter's noise margin is the most critical parameter, since it directly determines the maximum complexity of circuits.22 Particularly, interesting applications of organic electronic circuits are found in analog electronics that allow for the read-out and processing of signals from printed large-area sensors and form an interface to silicon electronics. Examples are analog-to-digital (A/D) converters, operational amplifiers, and comparators, all including several tens of transistors, thus requiring both high gain and a large noise margin to be functional as well as sufficient processability. It is interesting to note that the majority of organic complementary inverters already mentioned24-34, 36-40 relied on pentacene as the p-type semiconductor (14 incidences), fluorinated copper phthalocyanine (6 incidences), or N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (5 incidences) as the n-type material. On the contrary, the variation in gate dielectric materials that are used is much higher with an emphasis on hybrid dielectric systems. Hybrid systems allow accounting for both a high dielectric breakdown voltage and an engineered interface to the semiconductor. Moreover, the implementation of biodegradable and biocompatible materials represents a new niche in the organic electronics research, aimed to address the issues of cost and toxicity to humans and environment posed by nowadays electronics, a topic that was recently reviewed elsewhere.41-43 Accordingly, we have demonstrated the usage of a novel hybrid and biodegradable high-k gate dielectric material system based on a cellulose derivative for low-voltage complementary organic circuits with exceptional high noise margins.35 Previous work done in our laboratories demonstrated the fabrication feasibility of complex circuits, where the electrode patterning was performed by a self-aligned photolithography technique.44, 45 This process can easily be transferred to an anodized aluminum (Al2O3) + trimethylsilyl cellulose (TMSC) based bilayer system; the respective results will be published soon. To follow on this preliminary work we have developed an extraordinarily well-performing complementary inverter technology based on a hybrid dielectric composed of a bilayer of alumina (Al2O3) and trimethylsilyl cellulose (TMSC) and pentacene or C60 for the p-channel and the n-channel organic semiconductor, respectively. It outperforms any inverter reported so far with respect to the combination of excellent key parameters, such as record DC gain of above 500 V/V, low operation voltage of only 4 V, and large noise margin up to 92.5%. In order to clarify the origin for this high performance, special attention is given to the investigation of the semiconductor–dielectric interface, the semiconductor morphology, the nature of traps, the influence of mobility levels on the inverter performance and its long-term stability. This article is not meant to report new materials and systems, but rather find explanations and present a thorough analysis of the extraordinary performance of the cellulose derivative (TMSC) dielectric and the TMSC to semiconductor interface in organic field-effect transistors and simple inverter circuits. All OTFTs presented in this work have a bottom gate, top contact device architecture, as illustrated in Figure 1a. The transistor fabrication process is described in detail in the Experimental Section. The semiconducting layer is pentacene for p-type and C60 (fullerene) for n-type conduction. For the gate dielectric, an inorganic (Al2O3)–organic (TMSC) bilayer is chosen with 28 and 30 nm layer thickness, respectively. The dielectric properties of both single-layer TMSC films and bilayer Al2O3 + TMSC films, were investigated by current–voltage (I(V)), capacitance–frequency (C(f)), and capacitance–voltage (C(V)) measurements in appropriate capacitor structures with 72 nm insulator layer thickness of pure TMSC and 28 + 30 nm of bilayer film of Al2O3 + TMSC, respectively. In Figure 1b, the I(V) curves of a representative capacitor formed by a single layer cellulose dielectric is shown, whereas in Figure S1a (in the Supporting Information) the curve with bilayer dielectric is displayed. A comparison of I(V) curves of a single layer and bilayer dielectric is displayed in Figure 1c. At an electric field of 3.0 MV cm−1 (equivalent to ≈22 V) a current density on the order of 10−6 A cm−2 is observed for the single-layer TMSC. A breakdown field of 4.5 ± 0.3 MV cm−1 is extracted from eight appropriate capacitor structures. One representative C(V) measurement is displayed in Figure 1d. Its capacitance of about 29 nF cm−2 corresponds to a dielectric constant of εR = 2.4 ± 0.2 at 1 kHz with an excellent stability at frequencies down to 0.5 mHz (virtually flat dielectric constant and low dielectric losses which are indicative of a high purity and negligible amount of mobile ionic species) as illustrated in Figure 1e.46 In comparison, capacitors based on the bilayer dielectric have three orders of magnitude lower leakage currents (≈10−9 A cm−2) at an electric field of 3.0 MV cm−1 corresponding to ≈17.5 V and an effective capacitance of 53 nF cm−2 at 1 kHz (see Figure S1a,b, Supporting Information). As can be derived from Figure S1c (in the Supporting Information) the permittivity of the bilayer dielectric also shows excellent stability over the tested frequency range (1 mHz to 10 kHz). The measured capacitance value of the dielectric is in good agreement with calculations by assuming a permittivity of 9 and a thickness of 28 nm for the Al2O3 layer as well as a measured permittivity of 2.4 ± 0.2 (Figure 1e) and 30 nm thickness for the TMSC layer (see the Experimental Section). In any OTFT with bottom gate architecture the surface properties of the gate dielectric (surface energy, surface roughness) decisively affect the arrangement and growth of small molecule semiconductors. The surface energy of spin-coated TMSC thin films was determined by contact angle measurements. With a water contact angle of 98.5°, TMSC can be regarded as a hydrophobic, low energy surface material with a total surface energy of γ = 24.2 ± 0.6 mN m−1, separable in a small polar component γP = 1.8 ± 0.5 mN m−1 and a dispersive component γD = 22.4 ± 0.1 mN m−1. The average surface roughness, indicated by the root mean square (rms)–roughness values, was found to be only 0.77 ± 0.1 nm by atomic force microscopy (AFM) measurements. On this smooth and low energy TMSC surface, a small-grain growth mode with average grain sizes between 150 and 300 nm for pentacene (shown in Figure 1a) and 50 nm for C60 was observed by AFM measurements. In Figure 2, typical electrical characteristics of OTFTs with either C60 or pentacene as the semiconducting layer are plotted. Both p- and n-type transistors are based on the inorganic–organic bilayer gate dielectric composed of Al2O3 and TMSC. The output characteristics ID(VDS) are displayed in Figure 2a,b, whereas the transfer characteristics ID(VGS) are shown in Figure 2c,d. Both transistor types display very small hysteresis between forward and reverse voltage sweeps. The output characteristics show clear saturation, but for the pentacene-based OTFT a non-linear behavior of the drain current at very low drain voltages is observable (Figure 2b). Such an S-shape of the output curve has been already observed and reported for many different device configurations and has sometimes been attributed to a lateral field dependent contact resistance.47-55 In Table 1, the critical device parameters Von (onset voltage), Vthr (threshold voltage), S (subthreshold swing), μlin (charge carrier mobility in the linear regime), and μsat (charge carrier mobility in the saturation regime) are compiled and averaged over eight devices for each transistor type. On average, C60-based OTFTs show a charge carrier mobility of 0.7 cm2 V−1 s−1 in the saturation regime, a threshold voltage of 1.3 V, and a small subthreshold swing of 305 mV dec−1. Pentacene-based OTFTs have on average a mean threshold voltage of −4.7 V, a very small subthreshold swing of 225 mV dec−1, and a field-effect mobility of 0.22 cm2 V−1 s−1 in the saturation regime. The gate leakage currents are very low and in the range of 10−10 A. The balanced performance of our p- and n-type OTFTs, as well as the fact that both transistor types strictly behave as normally off transistors at zero applied gate voltage is a good base for integrating them in complementary organic inverters. A schematic image of such a complementary inverter circuit is displayed in Figure 3a together with the voltage transfer characteristics (VTCs) of a typical device and the static gain measured for operation voltages of VDD = 4, 5, 6, and 7 V. The inverter exhibits extraordinarily high small-signal gains; for all operation voltages, gains above 500 V/V are measured with a maximum value of about 1000 V/V for VDD = 7 V. The best performing device even has a maximum gain value of 1600 V/V. Moreover, a very sharp transition regime (ΔVin ≤ 40 mV) and a full rail-to-rail swing are observed. The extracted inverter parameters are compiled in Table 2. The switching threshold voltages VM are found to be very close to the ideal value of VDD/2 at all operation voltages with a nearly perfect fit (e.g., VM = 2.04 V at VDD = 4 V). In Figure 3b, the mismatches of the threshold voltages to the ideal values (ΔVM) are plotted as a function of VDD revealing a linear increase of ΔVM with the supply voltage. This means that the asymmetry of the VTCs increase with increasing the operation voltages. Additionally, the noise margins (NM) are plotted in Figure 3b as a function of VDD, illustrating the linear decrease of the NM with increasing operation voltage. Such a behavior reveals the direct correlation between ΔVM and NM and is an indication of the deviation of the VTCs from perfect symmetry. The noise margin is an important figure of merit of an inverter stage and measures the immunity against inevitable transistor parameter variations and electrical noise.56 There are several ways to determine the noise margin of an inverter. One convenient way is called the “maximum equal criterion” (MEC), where the NM is found by the maximum square that fits between inverter transition curve and the mirrored inverter curve as shown in Figure 3c.22, 35 The NM values for all the supplied voltages are listed in Table 2. The noise margin is mainly limited by the steepness of the transition ΔVin and the position of the switching threshold voltage VM (VM = Vin = Vout) as shown in Figure 3c. High and balanced noise margins are found when the ideal condition VM = VDD/2 is met, thus when VM = Vin =VDD/2 = Vout. The inverter in Figure 3c has a NM of 1.79, which is 90% of the maximum theoretical value for a supply voltage of 4 V, determined by the “maximum equal criterion.” Additionally, the “negative slope criteria” reveals a balanced NM of 1.85 V (92.5%) for a supply voltage of 4 V. The OTFTs with pentacene and C60 semiconductor layers (as used in the complementary inverters) were also analyzed with regard to their long-term stability. The dependence of their onset voltage and charge carrier mobility on the time period after preparation is plotted in Figure 4 based on measurements of at least five devices for each transistor type. The error bars display the standard deviations. p- and n-type devices exhibit an onset voltage shift of +1.3 and +0.95 V, respectively, over a period of 45 days. The main part of the shift occurred either after the first or after the second measurement and then the onset voltage shift tended to saturate. It seems that both pentacene- and fullerene-based devices stabilized their electrical properties after few days. Between day 8 and day 45 no significant change in the transfer characteristics was observed. Concerning the subthreshold swing, no significant change was observed over 45 days (S = 215 mV dec−1 (0 days), 210 mV dec−1 (8 days), and 225 mV dec−1 (45 days)) in the pentacene OTFTs, indicating that the interface trap density is stable. On the contrary, after 8 days an increase of the swing was observed for the C60 devices from 305 mV dec−1 (0 days), to 410 mV dec−1 (8 days), to 430 mV dec−1 (45 days). The mean value of the charge carrier mobility of the pentacene OTFTs showed no significant variation over 45 days: 0.22 cm2 V−1 s−1(fresh sample), 0.19 cm2 V−1 s−1 (after 8 days), 0.21 cm2 V−1 s−1 (after 45 days). In contrast, a strong reduction of about one order of magnitude (from 0.7 to 0.06 cm2 V−1 s−1 within the first 8 days and to 0.05 cm2 V−1 s−1 after 45 days) was observed for the fullerene transistors. In order to test the reliability of our OTFT devices we have also performed negative and positive bias stress tests. The bias stress was done 1 day after fabrication, on devices which had been previously measured only once. A reversible negative onset voltage shift of about 400 mV was observed under negative bias of −7.5 V over 21 hours stress (see Figure 5a,b) The main part of the negative voltage shift occurred during the first 2 hours (300 mV) whereas shift saturation was reached after 6 hours. The positive bias stress resulted in a significantly smaller positive onset voltage shift (ca. +100 mV over 4 hours stressing the device). Devices that were stored for seven months in the glovebox showed no bias stress effect at all (i.e., shift of the onset voltage) when their transistor characteristics were measured at regular intervals during the storage period. In order to investigate the “long-time” behavior of complementary inverters, electrical measurements were done after 1, 4, 8, and 45 days of the respective device preparation. Inverters were measured 1 day after device stabilization (see Figure 4a,b). The “long-time” behavior of complementary inverters is shown in Figure 4c,d where the VTC and gain curves are plotted as a function of time. For the lowest VDD of only 4 V, a small shift of the switching threshold voltage was measured: starting from 2.04 V after 1 day to an identical value of 2.17 V after 8 and 45 days, respectively, with a related exceptional high noise margin of 1.79 V (90% of the theoretical maximum) after 1 day and 1.74 V (87%) after 8 and 45 days. It is interesting to note that, after 8 days of storage time, the hysteresis in inverter characteristics was virtually negligible (<100 mV, see Figure 4d) and moreover, repeated measurements did not change the inverter transition, although the gain was somewhat reduced (from 503 (0 days) to 320 (8 days) and 195 (45 days)). The operational stability of the VTC was shown over a period of at least 45 days (Figure 4c for VDD = 4 V). Furthermore, the remarkable long-term stability of these TMSC-based complementary inverters was demonstrated by 16 consecutively recorded inverter curves that are virtually superimposed over one another (Figure 5c). The current–voltage characteristics show that the Al2O3 + TMSC bilayer capacitors have substantially lower leakage currents than the single TMSC layer devices. Due to the roughness of the aluminum bottom electrode with spikes up to 10 nm, the anodization process is a convenient method to reduce the leakage currents for at least three orders of magnitude at an electric field of 3 MV cm−1 as displayed in Figure 1d and make the dielectric layer more robust.57 Another advantage of the anodization step is the substitution of the hydroxide of the native oxide layer. Finally, the subsequent short oxygen plasma treatment (see the Experimental Section) is sufficiently removing all residuals left after the anodization process. This procedure allows for the generation of a pure and trap-reduced dielectric interface to the organic semiconductors, by measurements at low revealing a virtually flat permittivity in the mHz to kHz frequency range and low dielectric losses which both are indicative of a high purity and negligible amount of mobile ionic The generation of this excellent interface is in virtually hysteresis-free characteristics of all the One important that the performance of OTFTs, and in the charge carrier is the of the As shown by several the of the surface energy of the to that of the is one important the growth For a low surface energy material with a smooth surface TMSC, a growth mode is and with a rather high density and small grain sizes are formed (see Figure The high density of grain a significant decrease of the charge carrier since grain as charge On the a better between pentacene on low surface energy materials TMSC with and better reduce the of trap thus the mobility of charge in the In there is an between grain related and interface with regard to their influence on charge carrier The low subthreshold swing observed in all our pentacene-based OTFTs is indicative of a low interface trap density which the influence of the large grain trap density on the charge carrier Accordingly, a mobility 0.2 cm2 V−1 s−1 is observed in the p-type devices. In C60 films, the influence of on the charge carrier mobility is by far not as significant as in pentacene films, which is attributed to the of the fullerene In the pentacene OTFTs (see Figure a non-linear current increase in the linear regime of the ID(VDS) output characteristics is at higher gate have been in to such a which can be observed in bottom gate The explanations i) the of the charge carrier mobility for semiconductor ii) currents that the of the mobile by an effective under the drain and iii) large at the electrode from an energy between the work of contact material and semiconductor films, a gate or large contact are found in our of these it has been shown that a mobility in combination with a small contact in a non-linear drain voltage dependence of the current due to The from a of from trap and a dependence of on the drain A respective of the pentacene output curve in Figure the dependence in the regime 2 V, thus indicating that a mobility has to be The of any hysteresis in the I(V) curves and the low and value of the subthreshold swing a low density of interface in the pentacene are not for the observed and the of the as by the of the pentacene layer gives rise to which to a field dependence of the charge carrier This is all the more given that the pentacene grain sizes are 300 nm at a large density of grain As by Figure 4 the characteristics of both pentacene- and C60-based OTFTs show a positive onset voltage shifts storage which after a of measurements. The virtually subthreshold swing in pentacene as well as the negligible hysteresis as the origin of the On the contrary, it seems that trap are for the positive onset voltage shift in are either over time or during the first measurements by the applied positive gate be easily by the gate bias and therefore are not to the swing, but the small onset voltage in pentacene-based It has been reported by many that the of the of trap in pentacene trap also be due to such as at the a at the or a at the fabrication and transfer from the to the measurement stage the semiconductor layer and rise to such For oxygen can even the devices are to but transferred directly and measured in a glovebox with reduced oxygen and water have also observed that the of oxygen with pentacene is in the that these are under device operation with the of oxygen in the grain observed that the storage of devices in and their subsequent measurement in did not a change in their I(V) also observed that the storage time to the first measurement has influence on the device (i.e., on the onset voltage in this of and the first measurement the of to the of oxygen or with the which in a second are by Moreover, also are are not as in the as the (see and This an for the positive shift of the onset voltage between first and second measurement (Figure and also for the saturation of the onset voltage shift in In order to clarify which of are present in our we performed measurements on pentacene films (in and after storage in for (see Figure Supporting Information). storage under a small increase of the at energy is observed that can be attributed to the to and The analysis reveals an increase of the from 0.2 to At the position no change is that trap in our devices for bias stress and the positive onset voltage can mainly be attributed to It be that the of any mobility in pentacene OTFTs against an of pentacene both are to oxygen For the C60 transistors, one a strong decrease of the charge carrier mobility during 8 days of storage which is by all over the device grain This is a effect of The decrease in charge carrier mobility and the at the interface that the subthreshold swing is in a positive onset voltage shift of the C60 transistors. With respect to the complementary inverters, noise margin values beyond from the maximum theoretical value for all supply voltages are and the high operational of the OTFT devices. At a very low supply voltage of 4 V, our bilayer organic complementary inverters have a static gain of more than 500 V/V with a noise margin of 92.5%, which is already reported devices with architecture (see the of inverter performance given in 38 and also gain values above 1000 V/V values up to 1600 were measured for our devices. This is all the most as the charge carrier mobility values of the transistors are not thus the that the of the mobility values between p- and n-channel with the virtually hysteresis are the factors for high gain and high noise margin Accordingly, a mobility 1 be the the is not high ≤ it can be by and p-channel transistors with different In our the mobility is The static of a complementary inverter is determined by technology parameters, the parameters of p- and n-type transistors. A good of these parameters a good saturation of both output can to a significant increase of the gain A is shown in the Supporting Furthermore, high gain values are also determined by the interface An insulator with an low trap density (as this is the for is in having I(V) curves with virtually zero Accordingly, it is to measurements with a very high voltage small voltage thus one to the high gain value of the complementary inverter it by hysteresis The noise margin with increasing VDD due to their strong this is also for the of the VTCs by see Figure A for this behavior can be found in the bias stress that was observed for both types of transistors. The negative shift of Von under negative gate and the positive

Indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) have attracted much attention because of their high electron mobility values (> 10 cm2/Vs) and because they can be processed at low temperature to produce large-area displays with the potential of low production costs. The IGZO TFTs require smaller RC signal delay with shorter channel length for high-resolution display applications. Therefore, it’s necessary to use self-aligned top-gate (TG) oxide TFT structure with smaller channel length for high-resolution, high-speed, low-power, and narrow-bezel displays. The IGZO TFTs also need good electrical stability under positive/negative bias temperature stress (P/NBTS) with decent TFT properties for peripheral gate driver integrated large size organic light emitting diode (OLED) TVs. TG IGZO TFTs for display applications such as OLED TVs typically use longer channel length (> 4 µm) due to negative threshold voltage (Vth) shift and Vth non-uniformity issues with smaller channel length, which is mainly caused by hydrogen diffusion near source/drain regimes during device integration. We fabricated TG IGZO TFTs by using Applied Material’s CVD/PVD tools to achieve excellent electrical stability and Vth uniformity by balancing oxygen and hydrogen diffusion into oxide channel layer such as IGZO. Suppressing carrier densities at the interface between gate insulator (GI) and IGZO by increasing oxygen diffusion with IGZO pre-annealing in air and TFT post anneal in air, and by minimizing vacuum annealing impact during GI deposition makes the IGZO TFTs more resistive with more positive Vth shift. On the other hands, more hydrogen diffusion into IGZO from GI, ILD, and passivation layers during device integration or TFT post annealing makes the IGZO TFTs more conductive with more negative Vth shift and worse Vth uniformity, but it helps to improve electrical stability with smaller Vth shift under PBTS by passivating defects inside IGZO. Therefore, there is trade-off between Vth uniformity and electrical stability due to the dominance of the diffusion between oxygen and hydrogen. By balancing the diffusion of oxygen and hydrogen, the IGZO TFTs can minimize negative Vth shift even with shorter channel for high-resolution display applications and achieve good electrical stability for pixel and peripheral gate driver circuits integrated in display panel. We successfully demonstrated excellent electrical properties such as high mobility (µFE), low sub-threshold slope (SS), good threshold voltage (Vth) position, and low off-leakage current from TG IGZO TFTs. The positions of Vth can be optimized by controlling carrier densities at the interface between GI and IGZO during device integration even with different GI temperature and power (Fig. 1). Here, GI type A is deposited at a low temperature of 225 ºC with a high RF power of 2400 W. GI type B is deposited at a high temperature of 270 ºC with a high RF power of 2400 W. GI type C is deposited at a high temperature of 270 ºC with a low RF power of 1600 W. In order to investigate the channel length dependency of Vth, Vth values were extracted from transfer characteristics at VDS = +1 V with various TFTs by fixing channel width of 12 µm and varying the channel length from 10 µm down to 3 µm. The differences between maximum Vth and minimum Vth, Vth (Max–Min), from GI type A, B, and C are 0.35 V, 0.48 V, and 1.20 V, respectively. Total resistance in TFTs was extracted from the measured IDS values by varying VGS from 12 V to 20 V with channel length from 10 µm down to 5 µm by transmission line method. Extracted 2∆L, the difference between mask channel length and effective channel length, from GI type A, B, and C are 0.78 µm, 0.87 µm, and 1.05 µm, respectively. The IGZO TFTs with higher GI power show better TFT uniformity than lower power GI without notable negative Vth shift and non-uniformity even with shorter channel length from 10 µm down to 3 µm by minimizing hydrogen diffusion into IGZO (Fig. 2). The IGZO TFTs with lower GI power show better stability under PBTS due to more hydrogen diffusion into IGZO. On the other hands, the IGZO TFTs show better stability under both PBTS and NBTS with higher GI temperature than lower temperature GI due to more hydrogen diffusion into IGZO (Fig. 3). Therefore, high power/high temperature GI is preferred for high-resolution mobile/VR displays considering short channel length effect and low power/high temperature GI is preferred for gate driver integrated OLED TVs considering stability, especially PBTS. Figure 1

<?Pub Dtl=""?> We have investigated the total ionizing dose (TID) radiation effects in AlGaN/GaN MOS-HEMTs as a function of dose and radiation bias, and compared them with conventional HEMTs. Under 10 keV X-ray irradiation, two distinct regimes of threshold voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{th})$</tex> </formula> shifts have been revealed: a rapid <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$V_{th}$</tex></formula> shift at low doses <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$[&lt; {3}{\rm krad (SiO}_{2})]$</tex></formula> for both HEMTs and MOS-HEMTs, and an additional <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex></formula> shift only found in MOS-HEMTs for doses up to at least 2 Mrad <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$({\rm SiO}_{2})$</tex></formula> . The rapid <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex> </formula> shift anneals quickly and is a strong function of layer material. We attribute this portion of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex> </formula> shift to hole trapping in the AlGaN barrier layer. The <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{th}$</tex></formula> shift at high doses found only in MOS-HEMTs is attributed to hole trapping in the gate oxide. By comparing MOSFETs with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm HfO}_{2}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Al}_{2} {\rm O}_{3}$</tex></formula> gate dielectrics that are annealed during processing at various temperatures, we find that <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$500^{\circ}{\rm C}$</tex></formula> annealed <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm HfO}_{2}$</tex></formula> shows the most promising TID response.

This Letter presents tri-gate GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) with improved high-temperature performance for a monolithic integration platform, utilizing a low-damage digital recess technique. The fin structure followed by the multiple cycles of plasma oxidation and wet oxide removal process enables threshold voltage modulation from −9.1 V (D-mode) to +1.1 V (E-mode) in MIS-HEMTs, achieved by tuning the fin width between 800 and 56 nm on the same wafer. The E-mode device shows a low subthreshold swing of 76 mV/dec, a low on-resistance of 8.2 Ω·mm, and a low hysteresis of 26 mV. The E-mode device exhibits a small threshold voltage (Vth) shift of −0.13 V from room temperature up to 200 °C leading to logic inverters of stable characteristics with an inverter threshold voltage shift of only 0.16 V from 25 to 250 °C. These results validate the monolithic integration of tri-gate GaN to be promising for high-frequency and compact mixed-signal systems.

Threshold voltage model development of N+ pocket vertical junctionless TFET (V-JL-TFET) as a label free biosensor

Gallium phosphide (GaP) nanowire transistors were fabricated in back-gated structure, and their electrical characteristics were measured systematically in both air and vacuum. The transistors turn on typically between −5 and −7V in ambient air. However, a large threshold voltage (Vth) shift, ∼10V, toward negative gate bias was observed in vacuum. After the transistors were exposed to air for 48h, Vth returned to the similar value in ambient air, implying a reversible process. The rate of Vth shift slows down when they were exposed to N2 in comparison with that of air. The shift of Vth is believed to be related to the charge transfer from the surface of GaP nanowire to the physically adsorbed OH or oxygen. In addition, the observed Vth shift from the GaP nanowire transistors can be explained by the conventional n-channel depletion mode metal-oxide-semiconductor field-effect transistor.

Simulation based investigation of Recessed Dual-Gate MISHEMT on sapphire substrate has been presented in this work using ATLAS simulation software. Various DC performance parameters such as: threshold voltage shift, drain current and transconductance has been compared for different gate combinations. Threshold voltage variation is observed to be nearly same if gate1 is recessed only or both gates are recessed. Positive shift in threshold voltage has been observed as the depth of gate recess is increased from 0 nm to 8 nm. Enhancement in negative junction depth from 10 nm to 18 nm results in the shift in threshold voltage towards positive i.e. −3.5 V to −2.45 V. This improvement in threshold voltage is due to the reduction in barrier thickness with increase in negative junction depth. DC performance has also been evaluated for the device with high-k gate dielectric such as HfO2 and TiO2 for non-recessed and recessed device. The parameters like gate oxide and work function variation results in the shift of threshold voltage from −3.5 V to 0 V in recessed Dual-Gate MISHEMT.

The ESL type IGZO oxide semiconductor TFTs with high Vth uniformity of delta Vth less than 1V, and high reliability has been developed at BOE G8.5 for 55inch AMOLED TVs. The mobility was ~10 cm2/Vs, the threshold voltage (Vth) shifts of BTS were successfully reduced to less than 1V and the Vth shifts of hysteresis were less than 0.1V. Furthermore, 55inch AMOLED TVs based on ESL type IGZO TFTs were produced with external compensation circuits.

This study investigated the effects of fluorine (F) diffusion from a CYTOP passivation layer into amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The F contained in the CYTOP passivation layer was diffused into a-IGZO through 350 °C annealing. The similar ionic radii of F and oxygen (O) allowed the passivation of oxygen vacancy (Vo) and weakly bonded oxygen by F. As a result, the a-IGZO TFTs with CYTOP passivation were highly stable under various stresses. The threshold voltage (Vth) shifts of a-IGZO TFTs without CYTOP passivation and with CYTOP passivation under a negative bias stress test for 10 000 s were −6.7 V and −2.5 V, respectively. In addition, the Vth shifts of each device under a negative bias illumination stress test for 4000 s were −10.9 V and −5.3 V, respectively. This improvement was caused by a reduction of Vo and a widened band gap of a-IGZO through the F diffusion effect. In addition, the CYTOP passivation layer maintained excellent properties as a barrier against moisture after 350 °C annealing.

Modeling of bias-induced changes of organic field-effect transistor characteristics

The instability in the electrical properties of 4H-SiC(0001) C-face metal–oxide–semiconductor (MOS) systems processed by wet gate oxidation with H2 postoxidation annealing (POA) was characterized. Wet-oxidized 4H-SiC C-face MOS capacitors indicated a large flat-band voltage (Vfb) shift owing to gate-bias stressing, but a H2 POA process improved the Vfb shift significantly. The threshold voltage (Vth) shift of wet-oxidized 4H-SiC C-face MOS field-effect transistors was reduced greatly to one-tenth by using an appropriate H2 POA process. These samples also indicated a high channel mobility (µfe) of 70 cm2/(V·s). The coexistence of small Vth instability and high µfe was achieved.

In this work, we report on a thorough study of charge loss in embedded non volatile memories. We focused on the fast initial threshold voltage (Vth) shift, which occurs during the first minutes of data retention bake. Experiments were performed to have a better understanding of this phenomenon. As a result, we can predict the Vth shift of a cell baked at 250degC and evaluate its impact on product reliability. This is the first time that this reliability aspect is characterized with such a level of accuracy. Based on these observations, a physical model is proposed to describe the fast initial threshold voltage shift

Semi-on DC stress experiments were conducted on AlGaN/GaN high electron mobility transistors (HEMTs) to find the degradation mechanisms during stress. A positive shift in threshold voltage (VT) and an increase in drain series resistance (RD) were observed after semi-on DC stress on the tested HEMTs. It was found that there exists a close correlation between the degree of drain current degradation and the variation in VT and RD. Our analysis shows that the variation in VT is the main factor leading to the degradation of saturation drain current (IDS), while the increase in RD results in the initial degradation of IDS in linear region in the initial several hours stress time and then the degradation of VT plays more important role. Based on brief analysis, the electron trapping effect induced by gate leakage and the hot electron effect are ascribed to the degradation of drain current during semi-on DC stress. We suggest that electrons in the gate current captured by the traps in the AlGaN layer under the gate metal result in the positive shift in VT and the trapping effect in the gate—drain access region induced by the hot electron effect accounts for the increase in RD.

A multi-gate n-type In 0.53 Ga 0.47 As metal oxide semiconductor field effect transistor is fabricated using the gate first self-aligned method and air-bridge technology with an 8 nm thick Al 2 O 3 oxide layer. By scaling the gate length down to 200 nm, the effect of two different source/drain doping concentrations on device parameters such as threshold voltage, I on / I off ratio and subthreshold swing were investigated at room temperature. Increasing the value of the source/drain doping concentration revealed an enhancement in all investigated parameters. Sheet resistance and contact resistance values were improved as well. The negative shift in threshold voltage for shorter gate lengths was observed for both source/drain concentrations; however, the shift in threshold voltage was less (~0.4 V) for the higher source/drain doping concentration.

In this study, the environmental dependence of the electrical stability of solution-processed n-channel zinc tin oxide (ZTO) thin-film transistors (TFTs) is reported. Under a prolonged negative gate bias stress, a negative shift in threshold voltage occurs in atmospheric air, whereas a negligible positive shift in threshold voltage occurs under vacuum. In the positive bias-stress experiments, a positive shift in threshold voltage was invariably observed both in atmospheric air and under vacuum. In this study, the negative gate-bias-stress-induced instability in atmospheric air is explained through an internal potential in the ZTO semiconductor, which can be generated owing to the interplay between H2O molecules and majority carrier electrons at the surface of the ZTO film. The positive bias-stress-induced instability is ascribed to electron-trapping phenomenon in and around the TFT channel region, which can be further augmented in the presence of air O2 molecules. These results suggest that the interaction between majority carriers and air molecules will have crucial implications for a reliable operation of solution-processed ZTO TFTs.