Hybrid Architectures and Controllers for Low-Dropout Regulators

The low dropout regulator (LDO) is a key component in power management, providing an accurate and stable output voltage against line/load variations and power supply ripple. From a literature review, we found that conventional analog and digital LDOs still exhibit difficulties to achieve good transient response or power supply rejection under certain scenarios. Therefore, it is straightforward to combine them as a hybrid LDO, enjoying the benefits of both topologies. Then, we can classify the hybrid LDO as analog-assisted-digital (AAD) and digital-assisted-analog (DAA). This brief reviews comparatively previous works on AAD and DAA LDOs, summarizes their pros and cons, and discusses possible application scenarios.

A low quiescent current digital low-dropout (D-LDO) voltage regulator with fast-transient response time is proposed for self-powered wireless sensor applications operating at near/subthreshold supply voltage. The D-LDO regulator incorporates both hill-climbing and binary search algorithms (HCBS) in the control logic, thus leveraging on each other's strengths to minimize the output voltage's ripple and the quiescent current during the steady-state period as well as output voltage's spike and response time during the transition period. Additional features such as hysteresis mode control and freeze mode control are incorporated into the system to improve the performance of the D-LDO regulator. A dynamic comparator is proposed for the near/subthreshold supply voltage operation, which minimizes the voltage error and improves the maximum operating frequency. Fabricated in 130-nm CMOS technology, the D-LDO regulator regulates the output voltage ${V}_{{\rm OUT}}$ from 350 to 1150 mV, while the input supply voltage ${V}_{\text{IN}}$ ranges from 450 to 1200 mV. At a ${V}_{{\rm OUT}}$ of 450 mV, ${V}_{{\rm IN}}$ of 500 mV and an operating frequency of 10 MHz, the regulator delivers 1500- ${\mu }$ A load current with $I_{\text{QUIESCENT}}$ of 8.9 ${\mu }$ A and a transient response time of 1.6 ${\mu }$ s. The maximum current and power efficiencies reach 99.9% and 89.9%, respectively. The measured line regulation and load regulation are 1.6 and 0.6 mV/mA, respectively.

A quad-output elastic switched capacitor converter with four cores and per-core digital low dropout regulators (LDOs) is designed in 130nm CMOS. This design routes power on demand by sharing the total switching capacitance network across all the cores and delivering power to each core in a time interleaved manner. As the current demand of a core increases, more switching capacitance and switch area resources are automatically allotted to the core. In case of further power demand, if the power delivery module can no longer allocate further resources, then it autonomously changes the voltage conversion ratio till the demand is met. Measurements reveal 87% peak power efficiency and 2.5× increase in core-frequency range, thus enabling wider dynamic voltage and frequency scaling (DVFS).

Nowadays, the clean and responsive power management circuits for system-on-a-chip (SoC) are demanding. The SoC enters idle mode by lowering the supply voltage, which even though can extend the battery lifetime, severely challenges the operation of all-analog circuits. As supply voltage reaches near-, even sub-threshold region, all-analog low dropout regulator (LDO) which powers the SoC will have a degraded performance. The digital LDO (DLDO) emerges as a promising solution, by replacing the analog circuits with a wide-range-supply compatible digital controller and thus can realize fast response speed without compromising the power consumption. Nevertheless, there are remaining issues such as poor balance between speed and accuracy, and the sensitivity to process, voltage and temperature variations. In this thesis, circuit level innovations are conducted to overcome these limitations. A capacitor-less DLDO is designed featuring a multi-step switching scheme, as well as an adaptive pipeline control with asynchronous clocking, for area- and power-efficient utilization. The measured load transient response is in nanoseconds for a 500 mA step at 0.6-1.0 V input. However, voltage ripple due to undesirable level toggling is observed during multi-step switching. The second prototype eliminates such ripples by adopting a soft multi-step switching technique which enables a more accurate regulation. DLDOs tend to be more sensitive to the supply noise than their analog counterparts. Analog-assisted digital control is thus investigated to enhance the power supply rejection (PSR). As the auxiliary controller, an inverter-based amplifier (IBA) is designed with rail-to-rail common-mode operation and process-variation compensated trip-point control. The IBA-based LDO is designed, and achieves -20 dB PSR in the megahertz range at 0.2 V lowest supply voltage. This LDO pushes the limit of analog control, and is promising to assist the main regulator for PSR enhancement. All developed prototypes in this thesis are implemented using a standard 65-nm CMOS process.

Low-Dropout Regulators (LDOs) are commonly desired for fine-grained power management in SoCs because of their compact area, high current efficiency, and small output ripple. Digital LDOs (DLDOs) are increasingly adopted in recent years thanks to voltage and process scalability. However, achieving a fast response to a load change requires a conventional synchronous DLDO to either increase its sampling frequency with a large power overhead, or include a large output capacitor (COUT) with increased chip area and cost. Various control schemes have been proposed to mitigate these drawbacks. In synchronous designs, attempts have been made to employ more complex control algorithms to achieve faster response [1], and to replace the PMOS switch array with switched capacitors for reduced dynamic energy consumption [2]. On the other hand, asynchronous DLDOs with event-driven [3] and beat-frequency VCO-based structures [4] show promise across the key performance, power and area metrics. Recently, voltage regulators are also found to be useful in enhancing the resistance of cryptographic engines and processors against power and EM side-channel attacks (SCAs) [5]-[7], which are physical attacks representing a severe threat to mobile and embedded devices. Employing regulators for SCA defense is promising because they are already used in most systems and require no modifications to existing computing architectures and algorithms like other circuit-level defenses [8]-[9]. In this paper, we present a high-performance and SCA-aware DLDO leveraging the unique properties of the Edge-Chasing Quantizer (ECQ). The 65nm DLDO prototype achieves: 1) a 101.7mV droop and 506ns settling time after a 20mA, 0.1ns step load change, with only a 0.1nF capacitor; 2) a 0.018mm2 active area and 99.4% peak current efficiency; and, 3) more than 14000× improvement in power SCA resistance on a 128b AES engine, with 27.5% area, 19.4% power, and 4.54% performance overheads over a standalone AES, and negligible overhead when compared to an AES design integrated with conventional DLDOs.

Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, event-driven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

Dynamic voltage and frequency scaling (DVFS) is a means to adjust the computing capacity and power consumption of computing systems to the application demands. DVFS is generally useful to provide a compromise between computing demands and power consumption, especially in the areas of resource-constrained computing systems. Many modern processors support some form of DVFS. In this article, we focus on the development of an execution framework that provides lightweight DVFS support for reactive stream processing systems (RSPS). RSPs are a common form of embedded control systems, operating in direct response to inputs from their environment. At the execution framework, we focus on support for many-core scheduling for parallel execution of concurrent programs. We provide a DVFS strategy for RSPs that is simple and lightweight, to be used for dynamic adaptation of the power consumption at runtime. The simplicity of the DVFS strategy became possible by the sole focus on the application domain of RSPs. The presented DVFS strategy does not require specific assumptions about the message arrival rate or the underlying scheduling method. While DVFS is a very active field, in contrast to most existing research, our approach works also for platforms like many-core processors, where the power settings typically cannot be controlled individually for each computational unit. We also support dynamic scheduling with variable workload. While many research results are provided with simulators, in our approach, we present a parallel execution framework with experiments conducted on real hardware, using the single-chip cloud computer many-core processor. The results of our experimental evaluation confirm that our simple DVFS strategy provides potential for significant energy saving on RSPs.

A fully synthesizable digital low drop-out regulator (LDO) with dual (coarse/fine) loops control is proposed. This structure employs a synchronized comparator to compare the feedback voltage (Vfb) and the desired reference voltage (Vref). A coarse loop is used to simplify the control logic circuit and increase the LDO response speed during the output dynamic transit. A fine loop is used to minimize the output ripple voltage of the LDO in the steady-state. A dynamic detection circuit using dual offset comparators is employed to detect the output voltage variation. To minimize the current consumption, the switching frequency is scaled to 1/32 of original frequency in steady-state. The circuit is implemented by purely digital standard cells. Simulation results at 130nm CMOS technology shows that this structure can achieve a peak current efficiency of 99.9% using a 1 MHz clock and a 0.6 V supply.

Dynamic voltage and frequency scaling (DVFS) is commonly employed on modern superscalar processors to reduce energy when peak performance is not needed or allowed. As technology scales, the effectiveness of DVFS is limited by the shrinking viable supply voltage range. This work proposes dynamic core scaling (DCS) to extend performance-energy tradeoff capabilities in superscalar processors. DCS ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. Evaluations using an 8-way superscalar processor implemented on 45nm circuit infrastructure show that DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS saves an additional 20% of a full-size core's energy on average. At the minimum operating voltage, DVFS stops reducing energy, while DCS is still able to achieve an average of 46% further energy reduction.

Dynamic Voltage and Frequency Scaling (DVFS) approach is proposed to control the power consumption in devices of different types like from a small mobile device to a huge server. This paper aims to study the effect of parallel execution of two benchmark applications, one the Stanford Single Source benchmarks (lightweight parallel code) and, Stanford Parallel Applications for Shared Memory (SPLASH-2) programs (heavy real-time data streaming parallel applications that run on multi -core clusters) on DVFS for dark silicon ameliorating. Both these benchmarks executed on a gem5 Full System simulator, booting a linaro based linux kernel. To get a holistic big picture of the power and thermal properties of systems that run on DVFS, in addition to the control feature present in gem 5, a power-estimation framework used for the evaluation of the efficiency of various DVFS policies, the MCPAT and Hotspot is also employed. Based on the execution of Stanford workloads DVFS model is analyzed in terms of memory footprint and on other critical processor performance metrics, like running time per core, bus latency, number of read, writes, access time, cache hit or miss. The gem5 is extended with full DVFS support by the addition of a framework in which easy power-model integration can be done.

Dynamic Voltage and Frequency Scaling (DVFS) is widely used in today's mobile devices. Commonly adopted OS level DVFS policies usually operate with high sampling and adjustment frequency in order to compensate for the lack of information from applications. In this paper, we consider the application of video decoding and propose a method that enables DVFS at a coarse time granularity by taking advantage of application level semantics. Using machine learning, we build a prediction model for the choice of CPU frequency based on the estimated workload and the progress of execution. We show that with our method, the system is able to perform DVFS with a frequency of only around 1 Hz, abiding by the practical constraints imposed by existing operating systems, but still saves an average of 40.1% in energy consumption compared with the execution at nominal speed. Further, we argue that the law of diminishing returns applies if we increase the frequency at which DVFS operates, and thus it may be costly and impractical to perform application level DVFS at a very fine time granularity.

Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have necessitated system level thermal management solutions for multi-core systems. Dynamic thermal management (DTM) techniques monitor on-chip temperature continuously and typically employs dynamic voltage and frequency scaling (DVFS) to lower the temperature when it exceeds a pre-defined threshold. State-of-the-art DTM solutions for multi-core systems include distributed DVFS (where each core can scale the voltage/frequency individually) and global DVFS (where all cores scale voltage/frequency simultaneously). Distributed DVFS generally offers higher performance than global DVFS, but it is hard to implement and has major scalability issues.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

Graphics processor (GPU) architectures have evolved rapidly in recent years with increasing performance demanded by 3D graphics applications such as games. However, challenges exist in integrating complex GPUs into mobile devices because of power and energy constraints, motivating the need for energy efficiency in GPUs. While a significant amount of power optimisation research effort has concentrated on the CPU system, GPU power efficiency is a relatively new and important area because the power consumed by GPUs is similar in magnitude to CPU power. Power and energy efficiency can be introduced into GPUs at many different levels: 1) Hardware component level - queue structures, caches, filter arithmetic units, interconnection networks, processor cores, etc., can be optimised for power. 2) Algorithm level - the deep and complex graphics processing computation pipeline can be modified to be energy aware. Shader programs written by the user can be transformed to be energy aware. 3) System level - co-ordination at the level of task allocation, voltage and frequency scaling, etc., requires knowledge and control of several different GPU system components We outline two strategies for applying energy optimisations at different levels of granularity in a GPU: (1) Texture Filter Memory (TFM) - an energy-efficient addition to the texture memory hierarchy component; and (2) an overall system level Dynamic Voltage and Frequency Scaling (DVFS) based energy reduction strategy based on an accurate tile-level slack prediction. Texture Filter Memory is an augmentation of the standard GPU texture cache hierarchy. Instead of a regular data cache hierarchy, we employ a small first level register based structure that is optimised for the relatively predictable memory access stream in the texture filtering computation. Predictability of the memory access patterns leads us to reduce power by using a simpler register access structure. Power is saved by avoiding the expensive tag lookup and comparisons present in regular caches. Further, the texture filter memory is a very small structure, whose access energy is much smaller than a data cache of similar performance. Dynamic Voltage and Frequency Scaling, an established energy management technique, can be applied in GPUs by first predicting the workload in a given frame, and, where sufficient slack exists, lowering the voltage and frequency levels so as to save energy while still completing the work within the frame rendering deadline. We apply DVFS in a tiled graphics renderer, where the workload prediction and voltage/frequency adjustment is performed at a tile-level of granularity, which creates opportunities for on-the-fly correction of prediction inaccuracies, ensuring high frame rates while still delivering low power. Tile-level energy management schemes are distinctly superior to schemes that work at the granularity of the entire frame in terms of energy saving and quality of the rendering measured in terms of frames rendered per second. The prediction mechanism relies both on the history - workload observed for the tile in recent frames, as well as rank - a quantification of the tile workload based on the frame structure, consisting of geometry, pixel shading, texture, and raster operations workloads.

A 1V∼1.2V battery input, 0.4V∼0.6V output low-power all-digital power management unit (PMU) composed of a high-efficiency digital buck converter (DBC) and a fast-transient digital low drop-out (DLDO) regulator is developed for energy-efficient SoC applications. A fully integrated 2-to-1 switched-capacitor dc-dc converter is combined together to reduce the quiescent current of digital control circuits. The digital pulse width modulation (DPWM) with clock frequency gating further reduces the power consumption of buck converter in steady state. From experiment results, the peak power efficiency of the proposed buck converter is 90% with an output power range of 30μW to 3mW and the peak current efficiency of DLDO is 98.8% at 5mW. Moreover, the proposed DLDO achieves 92ns/130ns transition time in 60mV voltage step to dynamically scaling the voltage of supply voltage in digital circuits. This chip is designed and fabricated in 65nm CMOS process for verification.