Hybrid Continuous-Discrete Computer: from ISA to Microarchitecture

Abstract

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In this project, we design an instruction set architecture for a proposed hybrid continuous-discrete computer (HCDC) chip. The ISA harnesses the microarchitectural features and analog circuitry provided in the hardware. We describe the workloads that are suitable for the HCDC architecture. The underlying microarchitecture for the HCDC chip, including its controllers, datapaths, and interfaces to analog and digital functional units are specified in detail. We live in a world that is continuous: our eyes see scenes defined by continuous curves and intensities of colors, hear sounds formed by continuously varying pressure waves, and we sense velocity and temperature as continuous signals. In contrast, current computers operate in a discrete world, despite the continuous nature of the world at the scale our senses perceive. We finely divide time and space into quanta in order to model the real world on our digital computers. The inherent costs of digital computing have been acceptable because of digital computers exponential growth in computing power relative to energy consumption and size. However, as scaling in digital computers comes to an end, we must explore alternatives to digital, discrete computing.