Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis

This dissertation describes research activities broadly concerning the area of High-level synthesis (HLS), but more specifically, regarding the HLS-based design of energy-efficient hardware (HW) accelerators. HW accelerators, mostly implemented on FPGAs, are integral to the heterogeneous architectures employed in modern high performance computing (HPC) systems due to their ability to speed up the execution while dramatically reducing the energy consumption of computationally challenging portions of complex applications. Hence, the first activity was regarding an HLS-based approach to directly execute an OpenCL code on an FPGA instead of its traditional GPU-based counterpart. Modern FPGAs offer considerable computational capabilities while consuming significantly smaller as compared to high-end GPUs. Several different implementations of the K-Nearest Neighbor algorithm were considered on both FPGA- and GPU-based platforms and their performance was compared. FPGAs were generally more energy-efficient than the GPUs in all the test cases. Eventually, we were also able to get a faster (in terms of execution time) FPGA implementation by using an FPGA-specific OpenCL coding style and utilizing suitable HLS directives. The second activity was targeted towards the development of a methodology complementing HLS to automatically derive optimization directives (also known as power intent) from a system-level design description and use it to drive the design steps after HLS, by producing a directive file written using the common format (CPF) to achieve shut-off (PSO) in case of an ASIC design. The proposed LP-HLS methodology reduces the design effort by enabling designers to infer low information from the system-level description of a design rather than at the RTL. This methodology required a SystemC description of a generic management module to describe the design context of a HW module also modeled in SystemC, along with the development of a tool to automatically produce the CPF file to accomplish PSO. Several test cases were considered to validate the proposed methodology and the results demonstrated its ability to correctly extract the low information and apply it to achieve optimization in the backend flow.

K-Nearest Neighbor (kNN) is an efficient algorithm used in many applications, e.g., text categorization, data mining, and predictive analysis. Despite having a high computational complexity, kNN is a candidate for hardware acceleration since it is a parallelizable algorithm. This paper presents an efficient novel architecture and implementation for a kNN hardware accelerator targeting modern System-on-Chips (SoCs). The architecture adopts a selection-based sorter dedicated for kNN that outperforms traditional sorters in terms of hardware resources, time latency, and energy efficiency. The kNN architecture has been designed using High-Level Synthesis (HLS) and implemented on the Xilinx Zynqberry platform. Compared to similar state-of-the-art implementations, the proposed kNN provides speedups between $1.4\times $ and $875\times $ with 41% to 94% reductions in energy consumption. To further enhance the proposed architecture, algorithmic-level Approximate Computing Techniques (ACTs) have been applied. The proposed approximate kNN implementation accelerates the classification process by $2.3\times $ with an average reduced area size of 56% for a real-time tactile data processing case study. The approximate kNN consumes 69% less energy with an accuracy loss of less than 3% when compared to the proposed Exact kNN.

The energy efficiency of space heaters is rated by Annual Fuel Utilization Efficiency (AFUE) governed by the Department of Energy in the United States which is a simple ratio of usable heat and fuel usage of a single heating device. It doesn't consider the overall performance of the heating system including not only the heating devices but also the characteristics of the building in different applications. The current AFUE method calculates only the energy efficiency which is thermodynamics first law efficiency. In this research, the systematic efficiency of a heating system rather than simple device efficiency has been defined and investigated. The systematic efficiency considers the overall efficiency of the whole heating system and it varies in the different applications even though with the same heating device. So it represents the performance of the system more precisely. Analytical models have been built to calculate both the systematic energy efficiency and exergy efficiency, and to evaluate the systematic energy and exergy efficiency of heating systems for direct fired and indirect fired heaters. Efficiency performances of the systems with these two types of heaters are compared. Sensitivities of input parameters for systematic energy efficiency are studied to show the impact towards systematic energy efficiency. Indoor carbon dioxide concentration level of direct fired heating system is also studied. In a case study, results show that systematic energy efficiency of indirect fired heating system is always constant at heater device efficiency which is 80\% while systematic energy efficiency of direct fired heating system varies from 40%-92% under different condition (heat loss coefficient, ambient temperature and air change requirement), indicating that simple device efficiency is not capable to evaluate the overall performance of heating system. New efficiency method such as systematic energy efficiency used in this research is needed to better describe the performance of the heating system. Results of indoor carbon dioxide level of direct fired heating system, from 1000 to 4500 PPM under different conditions, show that indoor air quality needs to be considered while using direct fired heating.

Principal Component Analysis (PCA) is a widely used approach for dimensionality reduction in image processing. In microwave imaging, for example, it is used as an intermediate step toward image reconstruction. An FPGA hardware implementation of PCA is highly beneficial, especially as an accelerator for a low-cost embedded environment. In this paper we propose a flexible PCA hardware accelerator that can be used for different input data dimensions and input precisions. In addition, it supports both floating-point and fixed-point arithmetic representations. The target hardware is a ZYNQ SoC. We used High Level Synthesis (HLS) to quickly explore the design space and so to find the best implementation for a given setting of the application parameters and given the characteristics of the target hardware. We show the impact on performance of different hardware optimization techniques enabled by HLS. The proposed method outperforms a similar state-of-the-art HLS design in terms of latency and resource usage.

High-level synthesis (HLS) is of paramount importance to enable software developers to map critical computations to FPGA-based hardware accelerators. However, in order to generate efficient hardware accelerators one needs to apply significant code transformations and adequately use the directive-driven approach, part of most HLS tools. The code restructuring and directives needed are dependent not only of the characteristics of the input code but also of the HLS tools and target FPGAs. These aspects require a deep knowledge about the subjects involved and tend to exclude software developers. This paper presents our recent approach for automatic code restructuring targeting HLS tools. Our approach uses an unfolded graph representation, which can be generated from program execution traces, and graph-based optimizations, such as folding, to generate suitable HLS C code. In this paper, we describe the approach and the new optimizations proposed. We evaluate the approach with a number of representative kernels and the results show its capability to generating efficient hardware implementations only achievable using manual restructuring of the input software code and manual insertion of adequate HLS directives.

A common use for Field-Programmable Gate Arrays (FPGAs) is the implementation of hardware accelerators. A way of doing so is to specify the internal logic of such accelerators by using Hardware Description Languages (HDLs). However, HDLs rely on the expertise of developers and their knowledge about hardware development with FPGAs. Regarding this, efforts have been focused on developing High-level Synthesis (HLS) tools in an attempt to increase the overall abstraction level required for using FPGAs. However, the solutions presented by such tools are commonly considered inefficient in comparison to the ones achieved by a specialized hardware designer. An alternative solution to program FPGAs is the use of Domain- Specific Languages (DSLs), as they can provide higher abstraction levels than HDLs still allowing the developers to deal with specific issues leading to more efficient designs and not always covered by HLS tools. In this paper we present our recent work on a DSL named LALP (Language for Aggressive Loop Pipelining), which has been developed focusing on the development of FPGAbased, aggressively pipelined, hardware accelerators. We present the recent LALP extensions and the challenges we are facing regarding to the compilation of LALP to FPGAs.

Hardware accelerators are key to the efficiency and performance of system-on-chip (SoC) architectures. With high-level synthesis (HLS), designers can easily obtain several performance-cost trade-off implementations for each component of a complex hardware accelerator. However, navigating this design space in search of the Pareto-optimal implementations at the system level is a hard optimization task. We present COSMOS, an automatic methodology for the design-space exploration (DSE) of complex accelerators, that coordinates both HLS and memory optimization tools in a compositional way. First, thanks to the co-design of datapath and memory, COSMOS produces a large set of Pareto-optimal implementations for each component of the accelerator. Then, COSMOS leverages compositional design techniques to quickly converge to the desired trade-off point between cost and performance at the system level. When applied to the system-level design (SLD) of an accelerator for wide-area motion imagery (WAMI), COSMOS explores the design space as completely as an exhaustive search, but it reduces the number of invocations to the HLS tool by up to 14.6×.

With the expansion of Convolutional Neural Networks (CNNs) applications in various domains such as autonomous driving and real-time data processing, the demand for efficient computational resources has increased dramatically. Traditional computing platforms such as CPUs struggle to manage the complex and data-intensive tasks required by modern CNNs. This paper delves into the development and system optimization of dedicated hardware accelerators - GPUs, FPGAs, and ASICs to meet these demands. Through innovative architectural design and optimization techniques, these gas pedals improve computational speed and energy efficiency. Our study demonstrates that through these optimizations, the processing efficiency of hardware accelerators is significantly improved while energy consumption is effectively controlled, setting a new standard for the design of future hardware accelerators for convolutional neural networks. In addition, I discuss practical applications and future challenges, providing a comprehensive overview of current technologies and their potential development. This research highlights the critical role of advanced hardware accelerators in enabling the next generation of AI applications, ensuring technological advancement and sustainability in high-demand computing environments.

This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with the high degree of variability in the process and environmental factors. Our framework is based on using on-chip delay sensors to improve timing prediction. Given a placed netlist at the pre-silicon stage, an optimization procedure is described which automatically generates the sensors subject to an area budget and available whitespace on the layout, in the presence of process variations. Each sensor is then generated as a sequence of logic gates with an approximate location on the layout at the pre-silicon stage. The on-chip sensor delay is then measured to predict the delays of individual design paths with less pessimism. In our experiments, we show that custom on-chip sensors can significantly increase the rate of predicting if a specified set of paths are failing their timing requirements.

As today's computer architectures are becoming more and more heterogeneous, a plethora of options including CPUs, GPUs, DSPs, reconfigurable logic (FPGAs), and other application-specific processors come into consideration for close-to-sensor processing. Especially, in the domain of image processing on mobile devices, among numerous design challenges, a very stringent energy budget is of utmost importance, making embedded GPUs and FPGAs ideal targets for implementation. Recently, the HIPAcc framework was proposed as a means for automatic code generation of image processing algorithms for embedded GPUs, based on a Domain-Specific Language (DSL). Despite of huge advancements in High-Level Synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. As a remedy, in this work, we propose code generation techniques for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, numerous high-level transformations, and automatic test bench generation. We evaluate our approach by comparing the resulting hardware accelerators to existing frameworks in terms of performance and resource requirements. Moreover, we assess the achieved energy efficiency in contrast to software implementations, generated by HIPAcc from the same code base, executed on GPUs.

Field-Programmable Gate Array (FPGA) based hardware accelerators offer reconfigurability, performance, adaptability, and good energy efficiency. The majority of Convolutional Neural Network (CNN) based inference systems are initially developed using standardized frameworks like PyTorch, Tensor Flow, and more. These Python or Python-like models can be mapped on FPGAs to build accelerators. Mapping frameworks to port designs on an FPGA convert the CNN models to high-level languages like C/C++ or OpenCL so that standard tools like high-level synthesis can facilitate the mapping of models on an FPGA. The logic utilization and performance of FPGA-based accelerators are dependent on the CNN network parameters, architectural selection (data-flow, pipelined, etc.), and synthesis-based control of design generation. A scalable multi-layer CNN hardware accelerator is modeled in Vitis 2020 HLS tool. Early estimation of performance and hardware resources helps choose the best CNN network before those are executed for time-consuming high-level synthesis and physical design mapping for FPGAs. We present various Machine Learning (ML) models to estimate the Logic Utilization and Computation Time from the Python design descriptions of CNNs. Our results show a very successful and accurate estimation for performance and resource utilization over various multi-layer CNN networks in negligible time before running HLS synthesis.

Long error detection latency, the time elapsed from the occurrence of an error caused by a bug to its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation and debug techniques. Traditional post-silicon validation tests can incur very long error detection latencies of millions or even billions of clock cycles. An earlier technique called Quick Error Detection (QED) shortens error detection latencies to only few hundred (or thousand) clock cycles. However, software-only QED (i.e., QED implemented entirely in software) can result in significantly increased post-silicon validation test runtimes. We present a new technique called Fast QED that overcomes this drawback of software-only QED, while preserving the error detection latency and bug coverage benefits of software-only QED. Simulation results using an OpenSPARC T2-like multi-core SoC and bugs abstracted from multiple commercial multi-core SoCs demonstrate: 1. Fast QED achieves 4 orders of magnitude improvement in test runtime as compared to software-only QED, with only 0.4% increase in chip area; 2. Fast QED improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error detection latencies compared to software-only QED; and, 3. Fast QED improves bug coverage by up to 2-fold compared to non-QED tests (similar to software-only QED).

Video processing applications have become increasingly difficult to implement on hardware, owing to the complex computer vision algorithms involved. This paper presents a real-time video processing architecture based on hardware/software co-design that improves execution speed and reduces the time to market of applications. We have implemented this framework for handwritten digit recognition on the Zybo Zynq-7000 ARM/FPGA SoC using Vivado High Level Synthesis (HLS) and Xillybus tools. Histogram of Oriented Gradients (HOG) feature extraction algorithm has been optimised for hardware execution and acceleration techniques have been applied on Vivado HLS to achieve a speed up of 38.89 for the HOG algorithm and recognition accuracy of 95.6%. Low precision arithmetic along with our approximations for costly functions, produced this significant gain in throughput by reducing 90% of the hardware resources required with just a marginal accuracy reduction by 1%. An overall performance improvement of 77% is obtained through hardware/software co-design over software execution. The framework identified digits seamlessly in a real-time video stream at 30 frames per second and enabled high frame rate video processing.

In this paper, we are demonstrating the implementation flow of algorithms using deep Convolutional Neural Networks (CNN). Deploying CNNs solely on CPU-GPU based platforms deal with issues of high power consumption and comparatively slower processing speeds than hardware accelerators like FPGA. FPGA offers high parallel-processing capability, hardware re-configurability, reduced latency and low power consumption. To further improve flexibility in programming the hardware accelerator, we decided to use High Level Synthesis (HLS) tool based on OpenCL framework for development of our CNN model and implementing it on cloud. We are using Xilinx SDAccel development environment targeting Amazon’s AWS EC2 F1 instances. We are using Cloud based services for our model visualization on FPGAs. Cloud provides FPGA as a service with High Performance Computing (HPC) resources and enables us to deploy our optimized code on provided FPGA accelerated instance without need of buying an actual hardware. AWS EC2 F1 instance uses Xilinx Ultrascale+VU9P chip as a Hardware platform.

Efforts to leverage the benefits of Deep Learning(DL) models for performing inference in resource constrained embedded devices is very popular nowadays. Researchers worldwide are trying to come up with software and hardware accelerators that make pre-trained DL models suitable for running the inference phase in these devices. Apart from software and hardware accelerators, DL model partitioning and offloading to Cloud or Edge network servers is becoming more and more practicable with increasing importance of Edge Computing. DL inference workflow partitioning and offloading can augment software / hardware acceleration for improved latency and energy efficiency in resource constrained embedded systems. Efficacy of a computation offloading to system is dependent on proper profiling of timing and energy required for processing DL algorithms. In this work we implement a DL inference offloading system using Raspberry Pi 3 based robot vehicle with a hardware accelerator from Intel (Neural Compute Stick). We report the workload partitioning approach, detailed experimental results and performance improvements achieved. We demonstrate that the current approach of DL execution profiling without considering dynamic system load of the edge device results in sub-optimal partitioning of DL algorithm and provide a solution approach to that.