Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions

The schedulability analysis of real-time embedded systems requires worst case execution time (WCET) analysis for the individual tasks. Bounding WCET involves not only language-level program path analysis, but also modeling the performance impact of complex micro-architectural features present in modern processors. In this paper, we statically analyze the execution time of embedded software on processors with speculative execution. The speculation of conditional branch outcomes (branch prediction) significantly improves a program's execution time. Thus, accurate modeling of control speculation is important for calculating tight WCET estimates. We present a parameterized framework to model the different branch prediction schemes. We further consider the complex interaction between speculative execution and instruction cache performance, that is, the fact that speculatively executed blocks can generate additional cache hits/misses. We extend our modeling to capture this effect of branch prediction on cache performance. Starting with the control flow graph of a program, our technique uses integer linear programming to estimate the program's WCET. The accuracy of our method is demonstrated by tight estimates obtained on realistic benchmarks.

Timing correctness of hard real-time systems is guaranteed by schedulability analysis and worst-case execution time (WCET) analysis of programs. Traditional WCET analysis mainly deals with application programs and has achieved success in industry. Timing analysis of application programs along cannot guarantee correctness of complete systems consisting RTOS. WCET tools designed for application program analysis have been applied to analyze RTOS routines by several research groups, but poor WCET estimations have been reported. Timing analysis of real-time systems considering both applications and RTOS has not been fully studied. So we intend to give a survey of related work on WCET analysis of RTOS. By summarizing previous work, challenges of WCET analysis of complete real-time systems are presented, and some possible further research potentials are unleashed.

In hard real-time task systems where periodic and aperiodic tasks coexist, the object of task scheduling is to reduce the response time of the aperiodic tasks while meeting the deadline of periodic tasks. Total bandwidth server (TBS) and advanced TBS (ATBS) are used in dynamic priority systems. However, these methods are not optimal solutions because they use the worst-case execution time (WCET) or the estimation value of the actual execution time of the aperiodic tasks. This paper presents an online slack-stealing algorithm called SSML that can make significant response time reducing by modification of look-ahead earliest deadline first (laEDF) algorithm as the slack computation method. While the conventional slack-stealing method has a disadvantage that the slack amount of each frame must be calculated in advance, SSML calculates the slack when aperiodic tasks arrive. Our simulation results show that SSML outperforms the existing TBS based algorithms when the periodic task utilization is higher than 60%. Compared to ATBS with virtual release advancing (VRA), the proposed algorithm can reduce the response time up to about 75%. The performance advantage becomes much larger as the utilization increases. Moreover, it shows a small performance variation of response time for various task environments.

There is a growing interest in adopting object technologies for the development of real-time control systems. Several commercial tools, currently available, provide object-oriented modeling and design support for real-time control systems. While these products provide many useful facilities, such as visualization tools and automatic code generation, they are all weak in addressing the central characteristic of real-time control systems design, i.e., providing support for a designer to reason about timeliness properties. We believe an approach that integrates the advancements in both object modeling and design methods and real-time scheduling theory is the key to successful use of object technology for real-time software. Surprisingly several past approaches to integrate the two either restrict the object models, or do not allow sophisticated schedulability analysis techniques. This study shows how schedulability analysis can be integrated with UML for Real-Time (UML-RT) to deal with timing properties in real time control systems. More specifically, we develop the schedulability and feasibility analysis modeling for the external messages that may suffer release jitter due to being dispatched by a tick driven scheduler in real-time control system and we also develop the scheduliablity modeling for sporadic activities, where messages arrive sporadically then execute periodically for some bounded time. This method can be used to cope with timing constraints in realistic and complex real-time control systems. Using this method, a designer can quickly evaluate the impact of various implementation decisions on schedulability. In conjunction with automatic code-generation, we believe that this will greatly streamline the design and development of real-time control systems software.

The most important and necessary properties of embedded real-time systems, and the ways to achieve them, are explored. The basic and most important domains of real-time systems design are dealt with, starting with the processor and system hardware architectures, over operating systems, tasking and scheduling, high-level real-time programming languages, worst case execution time and schedulability analysis, to application design engineering and safety critical applications. Common misconceptions which are still strongly present in the control systems design are identified, guidelines for the consistent implementation are proposed and sample solutions in certain areas are presented.

Cache memories are commonly avoided in real-time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. This paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to the previously available CRMA (Cached RMA: cache effect is incorporated in the utilization based Rate Monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outperforms CRMA.

The adoption of High-Level Synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

In this article we give an overview of the worst-case execution time (WCET) analysis research performed by the WCET group of the ASTEC Competence Centre at Uppsala University. Knowing the WCET of a program is necessary when designing and verifying real-time systems. The WCET depends both on the program flow, such as loop iterations and function calls, and on hardware factors, such as caches and pipelines. WCET estimates should be both safe (no underestimation allowed) and tight (as little overestimation as possible). We have defined a modular architecture for a WCET tool, used both to identify the components of the overall WCET analysis problem, and as a starting point for the development of a WCET tool prototype. Within this framework we have proposed solutions to several key problems in WCET analysis, including representation and analysis of the control flow of programs, modeling of the behavior and timing of pipelines and other low-level timing aspects, integration of control flow information and low-level timing to obtain a safe and tight WCET estimate, and validation of our tools and methods. We have focussed on the needs of embedded real-time systems in designing our tools and directing our research. Our long-term goal is to provide WCET analysis as a part of the standard tool chain for embedded development (together with compilers, debuggers, and simulators). This is facilitated by our cooperation with the embedded systems programming-tools vendor IAR Systems.

The design of modern real-time systems not only needs to guarantee their timing correctness, but also involves other critical metrics such as control quality and energy consumption. As real-time systems become increasingly complex, there is an urgent need for efficient optimization techniques that can handle large-scale systems. However, the complexity of schedulability analysis often makes it difficult to be directly incorporated in standard optimization frameworks, and inefficient to be checked against a large number of candidate solutions. In this paper, we propose a novel optimization framework for the design of real-time systems. It leverages the sustainability of schedulability analysis that is applicable for a large class of real-time systems. It builds a counterexample-guided iterative procedure to efficiently learn from an unschedulable solution and rule out many similar ones. Compared to the state-of-the-art, the proposed framework may be ten times faster while providing solutions with the same quality.

Real-time control systems must adequately react to changes in system state within a time limit determined by the dynamics of the controlled system, otherwise their stability might be compromised. It is therefore essential to determine the Worst-Case Execution Time (WCET) of the control algorithms to verify that they will always be able to satisfy that constraint. However, WCET analysis is a complex process, requiring manual intervention, and the computed bounds are often grossly overestimated. We avoid the difficulties of WCET estimation by making use of the single-path paradigm for the implementation of the control algorithm for a quadcopter. By using single-path code we do not only replace the cumbersome WCET analysis with a single measurement, we simultaneously avoid the detrimental effects of response-time variability. We show that single-path code can be applied to real-time controllers and that it is practical for dramatically simplifying WCET analysis as well as eliminating variability in the execution time. Our results show that despite its apparent inefficiency, the WCET of single-path code on a time-predictable soft microprocessor rivals that of a state-of-the-art superscalar processor.

This chapter deals with Reconfigurable Uniprocessor embedded Real-Time Systems to be classically implemented by different OS tasks that we suppose independent, asynchronous, and periodic in order to meet functional and temporal properties described in user requirements. The authors define a schedulability algorithm for preemptable, asynchronous, and periodic reconfigurable task systems with arbitrary relative deadlines, scheduled on a uniprocessor by an optimal scheduling algorithm based on the EDF principles and on the dynamic reconfiguration. Two forms of automatic reconfigurations are assumed to be applied at run-time: Addition-Remove of tasks and just modifications of their temporal parameters: WCET and/or Periods. Nevertheless, when such a scenario is applied to save the system at the occurrence of hardware-software faults, or to improve its performance, some real-time properties can be violated. The authors define a new semantic of the reconfiguration where a crucial criterion to consider is the automatic improvement of the system’s feasibility at run-time by using an Intelligent Agent that automatically checks the system’s feasibility after any reconfiguration scenario to verify if all tasks meet the required deadlines. Indeed, if a reconfiguration scenario is applied at run-time, then the Intelligent Agent dynamically provides otherwise precious technical solutions for users to remove some tasks according to predefined heuristic (based on soft or hard task), or by modifying the Worst Case Execution Times (WCETs), periods, and/or deadlines of tasks that violate corresponding constraints by new ones, in order to meet deadlines and to minimize their response time. To handle all possible reconfiguration solutions, they propose an agent-based architecture that applies automatic reconfigurations in order to re-obtain the system’s feasibility and to satisfy user requirements. Therefore, the authors developed the tool RT-Reconfiguration to support these contributions that they apply to a Blackberry Bold 9700 and to a Volvo system as running example systems and we apply the Real-Time Simulator Cheddar to check the whole system behavior and to evaluate the performance of the algorithm (detailed descriptions are available at the Website: http://beru.univ-brest.fr/~singhoff/cheddar). The authors present simulations of this architecture where they evaluate the agent that they implemented. In addition, the authors present and discuss the results of experiments that compare the accuracy and the performance of their algorithm with others.

Most previous research done in probabilistic schedulability analysis assumes a known distribution of execution times for each task of a real-time application. This is however not trivial to determine it with a high level of confidence. Methods based on measurements are often biased since not in general exhaustive on all the possible execution paths, whereas methods based on static analysis are mostly worst-case execution time - WCET-oriented. Using static analysis, this work proposes a method to obtain probabilistic distributions of execution times. It assumes that the given real time application is divided into multiple tasks, whose source code is known. Ignoring in this paper hardware considerations and based only on the source code of the tasks, the proposed technique allows designers to associate to any execution path an execution time and a probability to go through this path. A source code example is presented to illustrate the method.

Scheduling tasks is an essential requirement in most real-time and embedded systems, but leads to unwanted central processing unit (CPU) overheads. The authors present a real-time schedulability algorithm for preemptable, asynchronous and periodic reconfigurable task systems with arbitrary relative deadlines, scheduled on a uniprocessor by an optimal scheduling algorithm based on the earliest deadline first (EDF) principles and on the dynamic reconfiguration. A reconfiguration scenario is assumed to be a dynamic automatic operation allowing addition, removal or update of operating system’s (OS) functional asynchronous tasks. When such a scenario is applied to save the system at the occurrence of hardware-software faults, or to improve its performance, some real-time properties can be violated. The authors propose an intelligent agent-based architecture where a software agent is used to satisfy the user requirements and to respect time constraints. The agent dynamically provides precious technical solutions for users when these constraints are not verified, by removing tasks according to predefined heuristic, or by modifying the worst case execution times (WCETs), periods, and deadlines of tasks in order to meet deadlines and to minimize their response time. They implement the agent to support these services which are applied to a Blackberry Bold 9700 and to a Volvo system and present and discuss the results of experiments.

Worst case execution time (WCET) analysis is essential for exposing timeliness defects when developing hard real-time systems. However, it is too late to fix timeliness defects cheaply since developers generally perform WCET analysis in a final verification phase. To help developers quickly identify real timeliness defects in an early programming phase, a novel interactive WCET prediction with warning for timeout risk is proposed. The novelty is that the approach not only fast estimates WCET based on a control flow tree (CFT), but also assesses the estimated WCET with a trusted level by a lightweight false path analysis. According to the trusted levels, corresponding warnings will be triggered once the estimated WCET exceeds a preset safe threshold. Hence developers can identify real timeliness defects more timely and efficiently. To this end, we first analyze the reasons of the overestimation of CFT-based WCET calculation; then we propose a trusted level model of timeout risks; for recognizing the structural patterns of timeout risks, we develop a risk data counting algorithm; and we also give some tactics for applying our approach more effectively. Experimental results show that our approach has almost the same running speed compared with the fast and interactive WCET analysis, but it saves more time in identifying real timeliness defects.

Foreword. Preface. Acknowledgments. 1. Introduction. 2. Polymorphic calls. 3. Software techniques for efficient polymorphic calls. 4. Row displacement compression of message dispatch tables. 5. Analysis of dispatch sequences on modern processor architectures. 6. Measurement of virtual function call overhead on modern processors. 7. Hardware techniques. 8. Basic indirect branch predictors. 9. Hybrid indirect branch predictors. 10. Related work. 11. Conclusions. 12. Glossary. 13. References. Appendices. Index.