I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems

Based on current trends, multicore processors will have 1000 cores or more within the next decade. However, their promise of increased performance will only be realized if their inherent scaling and programming challenges are overcome. Fortunately, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a reality—interconnect technology which can provide significantly more bandwidth at lower power than conventional electrical signaling. Optical interconnect has the potential to enable massive scaling and preserve familiar programming models in future multicore chips. This paper presents ATAC, a new multicore architecture with integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths. ATAC uses nanophotonic technology to implement a fast, efficient global broadcast network which helps address a number of the challenges that future multicores will face. ACKwise is a new directory-based cache coherence protocol that uses this broadcast mechanism to provide high performance and scalability. Based on 64-core and 1024-core simulations with Splash2, Parsec, and synthetic benchmarks, we show that ATAC with ACKwise out-performs a chip with conventional interconnect and cache coherence protocols. On 1024-core evaluations, ACKwise protocol on ATAC outperforms the best conventional cache coherence protocol on an electrical mesh network by 2.5x with Splash2 benchmarks and by 61% with synthetic benchmarks.

Computed tomography (CT) image reconstruction algorithms such as convolution backprojection (CBP) and the Fourier inversion method (FIM) are highly compute intensive applications for today's single processor systems. Shared memory multiprocessor systems are simple to implement. However the shared bus used to connect the processors to memory is a major bottleneck in a shared memory multiprocessor system. We have designed a hierarchical bus based system (HBBS) which solves the bus congestion problem by hierarchically increasing the number of buses. The architecture is truly expandable and it retains the simplicity of bus based systems. We have implemented the CBP and FIM algorithms on a HBBS, built using commercially available high performance floating point digital signal processor (DSP) devices. The HBBS is found to be efficient in executing the computed tomography (CT) image reconstruction algorithms. The motivation for this work is not to develop new algorithms, but to evaluate the relative performance of well known algorithms when applied to real practical architectures. The results show that an 8-node HBBS executes the CBP and FIM algorithms about 100 times faster compared to the execution time of CBP and FIM algorithms on an IBM 340 series Workstation.

In this paper, snoopy cache coherence protocols with update strategy have been studied, since description of protocols is apparently different in references, so we offer a common description in order to show simplicity and comparability protocols. Evaluating of protocols is in simulation level By limes simulator tools. Limes includes dragon protocol [1], that we added WTU and firefly protocols to it. As the simulation results show, precision of block sharing information in multiprocessor system, is major reason for different performance of update snoopy cache coherence protocols, so if this information amount to be high, then performance will be high, but on the other hand, implementation cost will be high, as well.

Scalability of cache coherence protocol is a key component in future shared-memory multi-core or multi-processor systems. The state space explosion is the first hurdle while applying model-checking to scalable protocols. In order to validate parameterized cache coherence protocols effectively, we present a new method of reducing the state space of parameterized systems, two-dimensional abstraction (TDA). Drawing inspiration from the design principle of parameterized systems, an abstract model of an unbounded system is constructed out of finite states. The mathematical principles underlying TDA is presented. Theoretical reasoning demonstrates that TDA is correct and sound. An example of parameterized cache coherence protocol based on MESI illustrates how to produce a much smaller abstract model by TDA. We also demonstrate the power of our method by applying it to various well-known classes of protocols. During the development of TH-1A supercomputer system, TDA was used to verify the coherence protocol in FT-1000 CPU and showed the potential advantages in reducing the verification complexity.

As the number of cores in a single chip increases, a typical implementation of coherence protocol adds significant hardware and complexity overhead. Besides, the performance of CMP system depends on the data access latency, which is highly affected by coherence protocol and on-chip interconnect. In this paper, we propose PPB (Phase-Priority Based) cache coherence protocol, an optimization of modern directory coherence protocol. We take advantage of the observation that transient states occur in directory coherence protocol, resulting in some unnecessary transient states and stalling. PPB cache coherence protocol decouples a coherence transaction and introduces the idea of phase message. This phase is considered as the priority of the message. Additionally, we also add new priority-based arbitrators in on-chip network to support PPB cache coherence protocol. This mechanism in on-chip network can support effective cache access, which makes the on-chip network more efficient. Our analysis on an execution-driven full system simulator using SPLASH-2 benchmark shows that PPB cache coherence outperforms a MESI based directory, and the number of unnecessary transient states and stalling reduces up to 24%. Also it reported the speedup of 7.4%. Other advantages of this strategy are reduced delay of flits and significantly less energy consumption in on-chip network.

This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's aggregate on-chip cache resources. Cooperative caching combines the strengths of private and shared cache organizations by forming an aggregate "shared" cache through cooperation among private caches. Locally active data are attracted to the private caches by their accessing processors to reduce remote on-chip references, while globally active data are cooperatively identified and kept in the aggregate cache to reduce off-chip accesses. Examples of cooperation include cache-to-cache transfers of clean data, replication-aware data replacement, and global replacement of inactive data. These policies can be implemented by modifying an existing cache replacement policy and cache coherence protocol, or by the new implementation of a directory-based protocol presented in this paper. Our evaluation using full-system simulation shows that cooperative caching achieves an off-chip miss rate similar to that of a shared cache, and a local cache hit rate similar to that of using private caches. Cooperative caching performs robustly over a range of system/cache sizes and memory latencies. For an 8-core CMP with 1MB L2 cache per core, the best cooperative caching scheme improves the performance of multithreaded commercial workloads by 5-11% compared with a shared cache and 4-38% compared with private caches. For a 4-core CMP running multiprogrammed SPEC2000 workloads, cooperative caching is on average 11% and 6% faster than shared and private cache organizations, respectively.

The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multi-processing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.

Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely degrade without hardware support for tracking taints. This paper observes that information flow tracking can be efficiently emulated using deferred exception tracking in microprocessors supporting speculative execution. Based on this observation, we propose SHIFT, a low-overhead, software-based dynamic information flow tracking system to detect a wide range of attacks. The key idea is to treat tainted state (describing untrusted data) as speculative state (describing deferred exceptions). SHIFT leverages existing architectural support for speculative execution to track tainted state in registers and needs to instrument only load and store instructions to track tainted state in memory using a bitmap, which results in significant performance advantages. Moreover, by decoupling mechanisms for taint tracking from security policies, SHIFT can detect a wide range of exploits, including high-level semantic attacks. We have implemented SHIFT using the Itanium processor, which has support for deferred exceptions, and by modifying GCC to instrument loads and stores. A security assessment shows that SHIFT can detect both low-level memory corruption exploits as well as high-level semantic attacks with no false positives. Performance measurements show that SHIFT incurs about 1% overhead for server applications. The performance slowdown for SPEC-INT2000 is 2.81X and 2.27X for tracking at byte-level and wordlevel respectively. Minor architectural improvements to the Itanium processor (adding three simple instructions) can reduce the performance slowdown down to 2.32X and 1.8X for byte-level and word-level tracking, respectively.

An approach to systematically update finite state protocols while preserving application independent properties such as consistency and executability is described. Protocols are modelled as a network of communicating finite state machines with each machine denoting the behavior of a single protocol controller. Updates to protocols are specified as a finite set of rules that may add, delete and/or replace one or more transitions in one or more controllers. Conditions on updates are identified under which a single transition in a single controller or multiple transitions in one or more controllers can be changed to produce an executable protocol with a consistent global transition relation. The effectiveness of the proposed approach is illustrated on a large class of cache coherence protocols. It is shown how several common design choices can be consistently incorporated into these protocols by specifying them as updates. Many changes to verified protocols are non-monotonic in the sense that they do not preserve all of the verified protocol invariants. The proposed approach enables incremental verification of application independent properties that need to be preserved by any update and are a precursor to verification of the application specific properties.

We present designs, theory and the results of fabrication and testing for a novel parallel microrobotic assembly scheme using stress-engineered MEMS microrobots. The robots are 240–280 μm × 60 μm × 7–20 μm in size, each robot consist of a curved, cantilevered steering arm, mounted on an untethered scratch drive actuator (USDA). These two components are fabricated monolithically from the same sheet of conductive polysilicon, and receive a global power-delivery and control signal through a capacitive coupling with an underlying electrical grid. However, only a single, global control signal can be used to maneuver multiple stress-engineered microrobots within the same operating environment. We show how only a single control and power delivery signal can be used to maneuver multiple microrobots to implement microassembly. We classify the robots into microrobot species based on the design of their steering arm actuators. The microrobot species are further classified as independent if they can be maneuvered independently using the global power and control signal. We show that microrobot species are independent if the two transition voltages of their steering arms, i.e. the voltages at which the arms are raised or lowered, form a unique pair. We present control algorithms that can be applied to groups of independent microrobot species to direct their motion from arbitrary non-deadlock configurations to desired planar microassemblies. We present designs and fabrication for four independent microrobot species, each with a unique transition voltage. The fabricated microrobots are used to demonstrate directed assembly of five types of planar structures from two classes of initial conditions, thereby validating our planning and control algorithms. We demonstrate an average docking accuracy of 5 μm, and use self-aligning compliant interaction between the microrobots to further align and stabilize the intermediate assemblies. The final assemblies match their target shapes on average 96%, by area.

BackgroundPooling is a cost effective way to collect data for genetic association studies, particularly for rare genetic variants. It is of interest to estimate the haplotype frequencies, which contain more information than single locus statistics. By viewing the pooled genotype data as incomplete data, the expectation-maximization (EM) algorithm is the natural algorithm to use, but it is computationally intensive. A recent proposal to reduce the computational burden is to make use of database information to form a list of frequently occurring haplotypes, and to restrict the haplotypes to come from this list only in implementing the EM algorithm. There is, however, the danger of using an incorrect list, and there may not be enough database information to form a list externally in some applications.ResultsWe investigate the possibility of creating an internal list from the data at hand. One way to form such a list is to collapse the observed total minor allele frequencies to “zero” or “at least one”, which is shown to have the desirable effect of amplifying the haplotype frequencies. To improve coverage, we propose ways to add and remove haplotypes from the list, and a benchmarking method to determine the frequency threshold for removing haplotypes. Simulation results show that the EM estimates based on a suitably augmented and trimmed collapsed data list (ATCDL) perform satisfactorily. In two scenarios involving 25 and 32 loci respectively, the EM-ATCDL estimates outperform the EM estimates based on other lists as well as the collapsed data maximum likelihood estimates.ConclusionsThe proposed augmented and trimmed CD list is a useful list for the EM algorithm to base upon in estimating the haplotype distributions of rare variants. It can handle more markers and larger pool size than existing methods, and the resulting EM-ATCDL estimates are more efficient than the EM estimates based on other lists.

The effect of HLA matching on one-year first cadaver donor graft survival rates between best and worst matches was 6% (P less than 0.001) for A, B; 7% (P less than 0.001) for DR; 9% (P less than 0.001) for A, DR; 15% (P less than 0.001) for B, DR; and 17% (P less than 0.001) for A, B, DR. For second cadaver donor grafts, the differences were comparable. Analysis of the cyclosporine-treated patients separately yielded similar results: 5% (NS) for A, B; 7% (P less than 0.001) for DR; 13% (P less than 0.001) for A, DR; 16% (P less than 0.001) for B, DR; and 18% (P less than 0.001) for A, B, DR. The most significant effect of matching was achieved by zero mismatching B and DR antigens. The one-year graft survival for patients with zero A, B, DR mismatch was 88% with cyclosporine. Without cyclosporine, zero mismatched A, B, DR grafts survive at 84%; this difference is not statistically significant. Zero mismatching for class I and II antigens (that is, A, DR or B, DR with cyclosporine) gives one-year graft survivals of 84% and 87%, respectively. The zero mismatching HLA class I and II antigen effect is lost when even one antigen is mismatched. Transfusions improved the one-year graft survival 10% in cyclosporine-treated patients, but not in those who were not treated with cyclosporine. Seventy-one patients transfused with more than 4 units of blood, zero B, DR mismatched, and treated with cyclosporine had a 91% one-year graft survival. Recipient pool sizes for obtaining zero A, B, DR or B, DR mismatched donors are calculated. Zero A, B, DR mismatched patients can be transplanted at a 19% frequency with a 10,000 recipient pool. The success rate for zero mismatching of class I and class II antigens indicates that kidney sharing and large recipient pool sizes are a reasonable policy.

Efficient solution of partial differential equations require a match between the algorithm and the target architecture. Many recent chip multiprocessors, CMPs (a.k.a. multi-core), feature low intra-thread communication costs and smaller per-thread caches compared to previous shared memory multi-processor systems. From an algorithmic point of view this means that data locality issues become more important than communication overheads. A fact that may require a re-evaluation of many existing algorithms.We have investigated parallel implementations of multi-grid methods using a parallel temporally blocked, naturally ordered smoother. Compared to the standard multigrid solution based on a red-black ordering, we improve the data locality often as much as ten times, while our use of a fine-grained locking scheme keeps the parallel efficiency high.Our algorithm was initially inspired by CMPs and it was surprising to see that our OpenMP multigrid implementation ran up to 40 percent faster than the standard red-black algorithm on a contemporary 8-way SMP system. Thanks to the temporal blocking introduced, our smoother implementation often allowed us to apply the smoother two times at the same cost as a single application of a red-black smoother. By executing our smoother on a 32-thread UltraSPARC T1 (Niagara) SMT/CMP and a simulated 32-way CMP we demonstrate that such architectures can tolerate the increased communication costs implied by the tradeoffs made in our implementation.

Current trends in microprocessor design are fundamentally changing the way that performance is extracted from computer systems. The previous programming model for sequential uniprocessor execution is being replaced quickly with a need to write software for tightly-coupled shared memory multiprocessor systems. Both academicians and business leaders have challenged programmers to update their skill sets and their tools to effectively tackle software development for these newer platforms [1].

Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hardware primitives such as compare-and-swap, load-linked/store-conditional and fetch-and-op, from which the higher-level synchronization operations are then implemented in software. Although the single-word hardware primitives are conceptually powerful enough to support higher-level synchronization, from the programmer's point of view they are not as useful as their generalizations to the multi-word objects.This paper presents two fast and reactive lock-free multi-word compare-and-swap algorithms. The algorithms dynamically measure the level of contention as well as the memory con.icts of the multi-word compare-and-swap operations, and in response, they react accordingly in order to guarantee good performance in a wide range of system conditions. The algorithms are non-blocking (lock-free), allowing in this way fast dynamical behavior. Experiments on thirty processors of a SGI Origin2000 multiprocessor show that both our algorithms react fast according to the contention variations and perform from two to nine times faster than the best known alternatives in all contention conditions.