Identifying 2-monotonic positive boolean functions in polynomial time

We consider the problem of identifying an unknown Boolean function f by asking an oracle the functional values $f(a)$ for a selected set of test vectors $a \in \{0,1\}^{n}$. Furthermore, we assume that f is a positive (or monotone) function of n variables. It is not yet known whether or not the whole task of generating test vectors and checking if the identification is completed can be carried out in polynomial time in n and m, where $m=|\min T(f)| + |\max F(f)|$ and $\min T(f)$ (respectively, $\max F(f))$ denotes the set of minimal true (respectively, maximal false) vectors of f. To partially answer this question, we propose here two polynomial-time algorithms that, given an unknown positive function f of n variables, decide whether or not f is 2-monotonic and, if f is 2-monotonic, output both sets $\min T(f)$ and $\max F(f)$. The first algorithm uses $O(nm^{2} + n^{2}m)$ time and $O(nm)$ queries, while the second one uses $O(n^{3}m)$ time and $O(n^{3}m)$ queries.

Given a positive Boolean function fand a subset δ of its variables, we give a combinatorial condition characterizing the existence of a prime implicant Dˆof the Boolean dual f d of f having the property that every variable in δ appears in Dˆ We show that the recognition of this property is an NP-complete problem, suggesting an inherent computational difficulty of Boolean dualization, independently of the size of the dual function. Finally it is shown that if the cardinality of δ is bounded by a constant, then the above recognition problem is polynomial. In particular, it follows that the co-ocurrence graph of the dual of a positive Boolean function can be always generated in time polynomial in the size of the function.

Reversible parallel computation: An evolving space-model

Light types for polynomial time computation in lambda calculus

Counting with rational generating functions

A graph-based approach to finding near-optimal output phase assignments for PLA minimization is presented. A distinctive feature of the approach is that it exploits the necessary and sufficient conditions to reduce the number of product terms needed for PLA implementation and permits the use of existing graph algorithms to solve the PLA output phase optimization problem. The work is based on the transformation of a PLA into a graph whose vertices are the set of conditions required to reduce each product term of the PLA, and whose edges represent the relations between these conditions. Cliques (completely connected subgraphs) in the graph correspond to the output phase assignments required to reduce the product terms represented by the vertices in the cliques. The optimal PLA output phase assignment problem is then formulated as the well-studied problem in graph theory: finding maximum cliques in graphs. Using an existing algorithm for locating cliques in graphs, a modified greedy algorithm is proposed to compute output phase assignments for logic functions in polynomial time. Experimental results using a number of benchmark functions show that the graph-based approach can achieve optimal or near-optimal output phase assignment for PLA minimization and can lead to PLA's with fewer product terms than achieved using existing approaches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Megiddo (Megiddo, N. 1979. Combinatorial optimization with rational objective functions. Math. Oper. Res. 4 414–424.) has proposed an algorithm to solve a class of combinatorial optimization problems with rational objective functions in polynomial time. The minimum ratio path problem is claimed to be one such problem. This claim is not correct as indicated below.

Due to the continuous shrinking of semiconductor technology, there are more and more subtle errors or faults widely distributed in manufactured chips, and traditional "single" stuck-at fault model may become inappropriate. It is definitely better if all combinations of multiple faults can be completely tested. In this paper, we present ATPG (Automatic Test Pattern Generation) techniques targeting all multiple stuck-at faults, i.e. all combinations of stuck-at faults. That is, given "n" possibly faulty locations in a circuit, the target set of faults consists of 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 fault combinations, as each possibly faulty location is under stuck-at 1, stuck-at 0, or normal/non-faulty. Traditional ATPG flows use fault simulators to eliminate all detectable faults by the current set of test vectors. The problem, however, fault simulators represent fault lists explicitly in the sense that all possible faults are enumerated in the fault lists. This prevents us from dealing with ultra large fault lists, such as 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 faults. We need "implicit" representation of faults in order to deal with such huge numbers of faults or fault combinations. We present SAT based formulations for ATPG of circuits having very large numbers of faults by implicitly eliminating detected faults. We solve a set of SAT problems whose constraints increase pure incrementally (here "pure" means never deleting constraints), and so the entire solving process can be very efficient, as all learnings obtained so far are valid in the following SAT problems. Experiments are performed on combinational parts of ISCAS89 circuits in their AIG (AND-Inverter Graph) representations. We have successfully generated the complete set of test vectors assuming that faults happen only at outputs of gates. Our ATPG techniques can also start with a given set of test vectors. If we start the ATPG processes with a set of test vectors for single stuck-at faults, we can obtain the set of additional test vectors required for multiple stuck-at faults. Results are a little bit surprising in the sense that we need very few additional test vectors for multiple faults, although the numbers of fault combinations are exponentially larger. As far as we know, for the first time, complete test vectors for all stuck-at faults for ISCAS89 circuits where faults happen only at outputs of gates in AIG representations of the circuits have been obtained.

Intensional Properties of Polygraphs

Weighted medians — positive Boolean functions conversion algorithms

The random logic portion of a chip Implementing a set of Boolean functions and sequential circuits usually represents a major contribution to chip area. Obviously, there are many circuits which realize the same Boolean function. Unfortunately, at present there is no general theory that provides designers (and design automation programs) with lower bounds for total area, for gate oxide area, and for delay time of logic Implementations in Integrated systems. Therefore, the main task for the computer optimization program appears In choice of the circuit with the most convenient layout.DIADES is a design automation system with register-transfer level description on its Input and CIF file on output [5]. The digital circuit can be described in both behavioral and structural mode. A set of successive compilations and hardware implementing and optimizing transformations create the description of the network on the level of logic gates and pass transistors. As the output of hardware compilation from the higher level, this description is usually nonoptimal and thus is next optimized by recursive technology independent transformations based on Boolean algebra (like A*O = O, A*A = A, etc.). Inverters are also inserted into long chains of AND or OR gates, being the results of iterative circuits' compilation [4].The next stages are: technology dependant optimization of the logic network, and network's layout. It is assumed that the resultant network is multilevel, consists of complex negative gates, and is realized in semiregular Weinberger-style gate matrix layout. The logic minimization method intended for layout minimization is described in this paper.It is assumed in our silicon compiler, that logic is constructed of n-channel, polysilicon gate MOSFET ratioless complex gates, performing any negative function. By negative function we understand negation of positive function, while positive function is any combination of AND and OR functors [1]. Functions for evaluation of circuit's performance parameters such as total area, area of gate oxide, and gate delay time are used. These functions are defined in terms of basic technology and selected topology parameters. The method can be adapted to other technologies.

In this paper, we show that checking some properties of Boolean functions which are given by the lists of monomials in their polynomial representations can be implemented in polynomial time. Multi-linear polynomials over GF(2) are often a convenient way to represent Boolean functions. There is a single polynomial for each Boolean function, and the length of the polynomial (i.e. the number of its monomials) which represents a function of n variables can be far less than 2n. Therefore, in some cases, polynomials are a compressed description of Boolean functions. Besides, polynomial representations of Boolean functions have applications in circuit lower bounds, computational learning, error-correcting codes, cryptography. We construct polynomial-time algorithms for checking some properties of Boolean functions which are given by the lists of monomials in their polynomial representations. The considered properties are self-anti-duality (evenness), self-duality, periodicity, 1-invariance (Mobius transform invariance, coincidence). Note that checking each of these properties directly by definition gives, in the general case, only exponential-time algorithms. The approach to construct our algorithms is the following. Firstly, we prove that if a Boolean function has a certain property then its polynomial has a special structure. And secondly, we check the property by its characterization, cutting negative cases by proven facts. More precisely, we analyze an exponential time algorithm and prove that if the number of steps of the algorithm exceeds a bound, which is polynomial in the input size, and may be computed in advance, then the input will be necessarily rejected.

Selection probabilities, viz. rank and sample selection probabilities, quantify the impulse suppression, robustness, lowpass filtering ability, and detail preserving ability of stack filters. Closed-form expressions exist for computing selection probabilities from positive Boolean function describing the stack filter. We first present an analysis framework that interprets a Boolean vector to denote membership in a partition set. Using this framework a new algorithm to compute selection probabilities from positive Boolean functions is derived. Next a method to synthesize a stack filter from specified selection probabilities is presented. An underdetermined system of linear Diophantine equations is derived in the unknown elements of the C-matrix and the desired selection probabilities. This system of equations is solved to obtain the candidate solutions for the C-matrix. For each candidate C-matrix, an algorithm based on partition sets is used to derive one or more positive Boolean functions of the stack filter or show that none exists.

Considers polynomial time testability of combinational circuits generated by input decomposition, especially those generated by the logic synthesis tool FACTOR. First, the complexity of the fault detection problem in this class of circuits is explored using a stuck-at fault model. An O(2/sup k/m) algorithm for detecting a single stuck-at fault is given that is faster than the O(16/sup k/m), previously reported best algorithm proposed by Fujiwara(1990), where k is the number of inputs in a subcircuit and m the number of signal lines in the circuit. Efficient, polynomial time algorithms are described for generating a test set for all single stuck-at faults in the circuit. The basic strategy is to eliminate backtracks during line justification by constructing tables or vector sets in each subcircuit, which makes the fault propagation procedure very simple and eventually results in an efficient test generation procedure. This presentation of efficient polynomial time test generation algorithms for FACTOR-generated circuits is important, since it shows that it is possible to synthesize circuits that are optimized for area and are polynomial time testable at the same time. >

A new fuzzy filter, called fuzzy stack filter (FSF), is proposed to extend the filtering capability of conventional stack filter (SF), which is based on the positive Boolean function (PBF) as its window operator. We fuzzify the onset and off-set of a given PBF to obtain two types of fuzzy PBFs. Then, we adopt the architecture of threshold decomposition to develop this new fuzzy filter with a fuzzy PBF as its window operator. Each fuzzy PBF is associated with a set of control parameters. Therefore, the original PBF can be estimated from above and below by two fuzzy PBFs with appropriate control parameters. Furthermore, we can apply the fuzzy modifiers to modify the fuzzy PBFs such that the PBFs can be completely estimated by the fuzzy PBFs. Hence, the stack filter is a special case of fuzzy stack filter. Since some control parameters are added in this new filter, the neural learning algorithms can be easily developed under the flexibility of the given control parameters. We first propose the fuzzy (m,n) rank-order filter to test our proposed learning algorithm. In this simple learning algorithm, we can remove the noise-corrupted images very well in contrast to the filtering behavior of rank-order filters. We believe that the results presented will lead to more fruitful research on more advanced and powerful learning algorithms dedicated to the appropriate applications.