- Book Chapter
- 10.5772/6245
New Digital Approach to CNN On-chip Implementation for Pattern Recognition
- Nov 01, 2008
- Daniela Durackova
There are many cases where image processing is performed using the neural network. The content of this Chapter is implementation of CNN (Cellular Neural Network) on a chip in a new original digital approach. First, testing of some features of the proposed cell of the neural network is evaluated. Then the design of the basic circuit containing the cell for the CNN will be introduced. The idea is to use it for a more complex chip with image processing application. CNN have been extensively used in various image processing applications. One of the most important problems in signal processing is noise removal. The input signals mostly arrive from the real world and therefore they contain relatively high amounts of noise. The CNN circuits are capable of removing this noise partly. The possibility of noise removing depends on the template (weight) coefficients between the cells. CNN networks are based on relatively simple principles, very similar to biological neurons. The input signals are multiplied by appropriate weights, the weight matrix being given intuitively, as it is typical for CNN networks. Then they are added and multiplied by the transfer function. We describe also the settings of weights coefficients. CNN have been extensively used in various image processing applications ( Matsumoto & Yokohama, 1990 ) or ( Sziranyi & Csicsvari, 1993 ). The main problem of CNN implementations on a chip is the chip area consumption. The most area is reserved for the multiplexer, so we looked for alternative multiplications. We describe the achieved results with the designed chip. During the creation of the chip architecture we proposed and introduced special original coding for the weight coefficients. After simulations we recognized that the results were better with rounding than without it, but we found that the rounding during multiplication was not as important as we previously expected. Therefore we decided – instead of a hardware multiplexer – to use multiplication realized by simple gate timing of the special signal. The circuit was designed as a digital synchronized circuit. For the design and simulation we used the Xilinx tool. The cell is based on sub-circuits as it will be shown in detail. The Chapter describes the designed circuit. We introduce also our novel simulator for the CNN using the program tool Visual Basic for Application, and its algorithm which was based on the same principle as the planned designed circuit. The network can process the patterns with 400 points of recognition. O pe n A cc es s D at ab as e w w w .ite ch on lin e. co m
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