Impact of Thermal Constraints on Multi-Core Architectures

Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better thermal/power scaling (many small cores dissipate less than a large and complex one), and the ease and reuse of design. This paper presents a thorough evaluation of multicore architectures. The architecture that we target is composed of a configurable number of cores, a memory hierarchy consisting of private L1, shared/private L2, and a shared bus interconnect. We consider a benchmark set composed of several parallel shared memory applications. We explore the design space related to the number of cores, L2 cache size, and processor complexity, showing the behavior of the different configurations/applications with respect to performance, energy consumption, and temperature. Design trade-offs are analyzed, stressing the interdependency of the metrics and design factors. In particular, we evaluate several chip floorplans. Their power/thermal characteristics are analyzed, showing the importance of considering thermal effects at the architectural level to achieve the best design choice.

This study examines vectorized programming for finite impulse response image filtering. Finite impulse response image filtering occupies a fundamental place in image processing, and has several approximated acceleration algorithms. However, no sophisticated method of acceleration exists for parameter adaptive filters or any other complex filter. For this case, simple subsampling with code optimization is a unique solution. Under the current Moore’s law, increases in central processing unit frequency have stopped. Moreover, the usage of more and more transistors is becoming insuperably complex due to power and thermal constraints. Most central processing units have multi-core architectures, complicated cache memories, and short vector processing units. This change has complicated vectorized programming. Therefore, we first organize vectorization patterns of vectorized programming to highlight the computing performance of central processing units by revisiting the general finite impulse response filtering. Furthermore, we propose a new vectorization pattern of vectorized programming and term it as loop vectorization. Moreover, these vectorization patterns mesh well with the acceleration method of subsampling of kernels for general finite impulse response filters. Experimental results reveal that the vectorization patterns are appropriate for general finite impulse response filtering. A new vectorization pattern with kernel subsampling is found to be effective for various filters. These include Gaussian range filtering, bilateral filtering, adaptive Gaussian filtering, randomly-kernel-subsampled Gaussian range filtering, randomly-kernel-subsampled bilateral filtering, and randomly-kernel-subsampled adaptive Gaussian filtering.

Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Excessive junction temperature reduces reliability and can lead to catastrophic failure. We examine the use of activity migration which reduces peak junction temperature by moving computation between multiple replicated units. Using a thermal model that includes the temperature dependence of leakage power, we show that sustainable power dissipation can be increased by nearly a factor of two for a given junction temperature limit. Alternatively, peak die temperature can be reduced by 12.4°C at the same clock frequency. The model predicts that migration intervals of around 20--200 are required to achieve the maximum sustainable power increase. We evaluate several different forms of replication and migration policy control.

As processor power density has increased at an alarming rate, chip/core temperature control becomes critical in satisfying given thermal constraint and avoiding hotspots. Unlike "run-to-finish" applications whose temperature will simply rise to saturation point and then stabilize, network applications do periodic packet processing, which causes temperature to rise and fall over time. However, no existing studies have focused on characterizing the temperature variation for periodic tasks. We envision that volatile thermal behavior has to be well understood in order to optimize thermal management. In this paper, we first build a novel predictive thermal model for generic periodic tasks running on a single core. This model can dynamically derive the core temperature at any time quickly and accurately. To verify the model, we use both Hot Spot simulator and a real Linux machine to run six network applications chosen from Net Bench. Then, we propose an online model update strategy using on-chip thermal sensors, which can effectively correct incidental errors by adjusting model parameters "on-the-fly". Finally, by combining the thermal model and the online update, we design, implement and evaluate a predictive model-based thermal management scheme on an Intel Xeon E5335 core for network applications based on the Stop & Go technique. Compared with two other alternatives, our scheme achieves lower temperature, higher throughput, no thermal constraint violation, and negligible overhead cost.

Overheating is a major issue especially in metal Additive Manufacturing (AM) processes, leading to poor surface quality, lack of dimensional precision, inferior performance and/or build failures. A 3D density-based topology optimization (TO) method is presented which addresses the issue of local overheating during metal AM. This is achieved by integrating a simplified AM thermal model and a thermal constraint within the optimization loop. The simplified model, recently presented in literature, offers significant computational gains while preserving the ability of overheating detection. The novel thermal constraint ensures that the overheating risk of optimized designs is reduced. This is fundamentally different from commonly used geometry-based TO methods which impose a geometric constraint on overhangs. Instead, the proposed approach takes the process physics into account. The proposed method is validated via an experimental comparative study. Optical tomography (OT) is used for in-situ monitoring of process conditions during fabrication and obtained data is used for evaluation of overheating tendencies. The novel TO method is compared with two other methods: standard TO and TO with geometric overhang control. The experimental data reveals that the novel physics-based TO design experienced less overheating during the build as compared to the two classical designs. A study further investigated the correlation between overheating observed by high OT values and the defect of porosity. It shows that overheated regions indeed show higher defect of porosity. This suggests that geometry-based guidelines, although enhance printability, may not be sufficient for eliminating overheating issues and related defects. Instead, the proposed physics-based method is able to deliver efficient designs with reduced risk of overheating.

<div class="htmlview paragraph">Cassini, NASA's mission to investigate the Saturnian system was launched successfully on October 15, 1997. The cruise period from launch until Saturn arrival takes the spacecraft through a wide range of solar/thermal environments (0.67 astronomical units [AU] to 10 AU). The thermal control approach, which consists of thermal design features and operational constraints, must therefore maintain hardware temperature limits throughout this wide range of environments.</div> <div class="htmlview paragraph">The off-sun exposure flight experience with interplanetary spacecraft at relatively close heliocentric distance is very limited. Cassini's ability to perform off-sun maneuvers relies heavily on the large thermal capacitance of the spacecraft's central body and the relatively short off-sun durations required for these maneuvers. The post launch execution of the first trajectory correction maneuver (TCM-1) was the first opportunity to validate the spacecraft off-sun capability and to enhance the thermal math model simulation capability.</div>

This paper describes a motor-converter design methodology, improving electric vehicles performances (EVP) such as autonomy, power to weight ratio and ripple torque under several physical, thermal and technological constraints. This methodology rests on the coupling of a parameterized analytical model of all the motor-converter to a software based on genetic algorithms method to optimize parameters influencing the EV P on circulation mission by respecting several physical and technological constraints of electric vehicles. The developed analytical model covering several motor configurations is validated by the finite elements and experimental methods [1, 2].

Integration of multi-objective reliability-based design optimization into thermal energy management: Application on phase change material-based heat sinks

Mass minimization and sensitivity analysis of high power modular multilevel converter

This paper summarizes the thermal challenges in conventional 3-D stacks and proposes a novel stacking structure that eases the thermal problem. The objective of this paper is first to define limits and opportunities for developing different 3-D chip stacks from a thermal perspective, and second to explore our proposed system as a function of microbumps, through silicon vias, die thickness, and other design parameters. In our proposed 3-D stack, the interposer integrated microfluidic heat sink serves as the main heat sink. To thermally decouple stacked dice, we propose air gap isolation between them and a thermal bridge on top of the stack to cool down the isolated die. To evaluate the thermal benefits of the stack, a thermal model is developed based on the finite difference method. Several chip stack scenarios are studied and the simulations are conducted with a processor power of 74.63 W/cm 2 and memory power of 2.82 W/cm 2 . The proposed architecture yielded processor and memory temperatures of 64°C and 40°C, respectively, compared with 76°C and 75°C for the air cooled stack.

This paper investigates the thermal operating capability of an interior permanent magnet synchronous machine. An iterative workflow is presented, combining electromagnetic modeling, control, power‐loss modeling, and thermal modeling to identify maximum thermal stable operating points. Special attention is given to the critical temperatures of winding and permanent magnets. A nonlinear reduced order model based on finite element method model was used to simulate the system, including an inverter model with space vector pulse width modulation in combination with field‐oriented control. Furthermore, an advanced iron core loss model and thermal lumped parameter model were employed. The presented approach allows for evaluating losses and their impact on steady‐state temperatures. The obtained results highlight the significant influence of space vector pulse width modulation on iron core losses and the importance of considering both advanced power‐loss models and adequate thermal models when analyzing the machine's thermal state. This research emphasizes the concept of a thermally stable envelope, providing a comprehensive understanding of the thermal boundaries under various operating conditions.

Twenty pure metals were considered as potential candidates for first-wall coatings of ICF reactor chambers. Seven were found to merit further consideration based on the results of computer-code calculations of figures-of-merit. The seven are rhenium, iridium, molybdenum, chromium, tungsten, tantalum, and niobium (listed in order of decreasing values of figures-of-merit). The calculations are based on mechanical, thermal, and vacuum vaporization engineering constraints. A number of alloys of these seven metals are suggested as additional candidates.

As technology scales, thermal management for multicore architectures becomes a critical challenge due to increasing power density. Existing power budgeting techniques focus on maximizing performance under a given power budget by optimizing the core configurations. In multicore era, a chip-wide power budget, however, is not sufficient to ensure thermal constraints because the thermal sustainable power capacity varies with different threading strategies and core configurations. In this article, we propose two models to dynamically estimate the thermal sustainable power capacity in homogeneous multicore systems: uniform power model and nonuniform power model . These two models convert the thermal effect of threading strategies and core configurations into power capacity, which provide a context-based core power capacity for power budgeting. Based on these models, we introduce a power budgeting framework aiming to improve the performance within thermal constraints, named as TSocket. Compared to the chip-wide power budgeting solution, TSocket shows 19% average performance improvement for the PARSEC benchmarks in single program scenario and up to 11% performance improvement in multiprogram scenario. The performance improvement is achieved by reducing thermal violations and exploring thermal headrooms.

Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. CMP is becoming important by delivering more compute performance within the power constraints. Dynamic Voltage and Frequency Scaling (DVFS) has been studied in past work as a mean to increase save power and improving the overall processor's performance while meeting the total power and/or thermal constraints. For such systems, power delivery limitations are becoming a significant practical design consideration, unfortunately this aspect of the design was almost ignored by many research works. This paper explores the various possible topologies to build a high end multi-core CPU and the available policies that maximize performance within the set of physical limitations. It evaluates single and multiple voltage and frequency domains and introduces a new clustered topology, grouping several cores together. A hybrid model, using measurements of a real CPU, cycle accurate simulator and an analytical model is introduced. The results presented indicate that considering power delivery limitations diverts the conclusions when such limitations are ignored. This paper shows that a single power domain topology performs up to 30% better than multiple power domains on light-threaded workload. In the fully threaded application the results divert. Clustered topology performs well for any number of threads.

Breaking boundaries in transistor technology has allowed the increase in the number of cores within a single chip. This, in turn, enables High-Performance Computing (HPC) systems with better capabilities to exploit thread-level parallelism (TLP). However, this also leads to unforeseen issues related to the temperature of these systems. Reaching high temperatures speeds up the aging process of hardware components by influencing their causes (e.g., negative bias temperature instability – NBTI), and that is not only dependent on the number of cores, but also the distance between them and their usage. On top of that, parallel applications present various patterns, such as irregularity, unbalanced computations, or high rates of communications. These different characteristics may accentuate such adverse effects. Given these considerations, we propose the aging-aware thread scheduling (AATS) optimization strategy that automatically finds the ideal combination of TLP exploitation and thread allocation strategy to execute applications with a key objective: improve the trade-off between performance and processor aging so the number of times an application may execute until the processor’s end-of-life is maximized. With the execution of thirteen well-known benchmarks on three different multicore architectures, we demonstrate that AATS converges to an ideal or near-ideal solution spending only 4.74% of the time spent by a design space exploration that tries all possible combinations. We also show that processor lifetime can be significantly extended when running applications with the solution found by AATS.