Impact of Turn-Off Semiconductor Devices on Power Electronics

Chapter 2 - Power Semiconductors

The purpose of this paper is to provide an insight into the present state of MOS-controlled thyristor (MCT) development as reflected in measured device terminal characteristics. User-oriented information regarding MCT circuit utilization is presented by focusing on the measured characteristics of a particular batch of MCTs (80 A, 500 V) fabricated in 1988. Measurements confirm the appealingly low forward voltage drop of the MCTs (1.1 V at 200 A/cm/sup 2/, 1500 degrees C). To increase current handling capabilities, eight matched devices have been paralleled to switch 600 A at 275 V (peak), representing a modest 6% device current derating. Measured MCT turn on is faster than turn off, which is dominated by internal charge recombination characteristics. Safe operating area and di/dt limits of the tested MCTs are discussed. Comparison with insulated-gate bipolar transistors (IGBTs) indicates that MCTs offer clear advantages for minimizing on-state conduction losses (approximately 3:1 at 150 degrees C), whereas switching times of new MCTs are as low as those of comparable IGBTs. >

Measurements have been made evaluating the switching and conduction characteristics of the first commercially available 600-V MCT (MOS controlled thyristor), the second-generation, 600-V MCT still under development, and a fast commercially N-IGBT (insulated-gate bipolar transistor). The data presented indicate that great strides have been made in improving the electrical performance of the P-MCT in the generation 2 device. Using the fmax curve as a figure of merit, the lower switching losses of the N-IGBT are favorable, under the test conditions used, compared to the generation 1 P-MCT up to approximately 50 A. The lower conduction losses of the MCT become the predominant factor for larger current levels. The generation 2 P-MCT combines the same conduction loss characteristics as its predecessor, with drastic reductions in turn-off switching times and losses. The combined effect gives the generation 2 P-MCT the lowest losses over the whole current and frequency range evaluated. The N-IGBT provides a better safe operating area than either of the P-MCTs, though capacitive snubbers can be employed to improve this situation. >

Measured and simulated turn-off curves of high-voltage MCTs (MOS-controlled thyristors) and IGBTs (insulated-gate bipolar transistors) are presented. Device simulation results show that the inherently faster-switching IGBT is much more affected by dynamic avalanche phenomena than the MCT. It is also shown that the avalanche-injected carriers can be removed by shorting the anode layer, resulting in a much higher turn-off performance for both devices. Because of the lower charge and therefore the higher dV/dt, the ionization rate is higher in the IGBT than in the MCT. >

Since the introduction of silicon-based thyristors in 1957, researchers in the field of power semiconductor devices have achieved remarkable progress. In the late 1960s, the gate turn-off thyristor (GTO) made it possible to turn off the latching thyristor devices using their gate terminals, enabling switching frequencies exceeding 1 kHz. In the mid-1970s, new silicon bipolar junction transistors and metal-oxide-semiconductor field-effect transistors (MOSFET) were introduced, pushing switching frequencies upward above 10 kHz. The insulated-gate bipolar transistor (IGBT) was developed in the 1980s with combined features of the MOSFET and bipolar transistor that made it an appealing choice for many power electronics applications, including motor drives. Today, IGBTs are the dominant power switching devices for power electronic converters operating at voltages greater than 600 Vdc.

An attempt was made to simplify the processing of MCT (MOS controlled thyristor) and IGBT (insulated-gate bipolar transistor) devices by combining the anneal of the p/sup +/-emitter with the gate oxidation process. A high-dose boron implantation prior to the gate oxidation is found to be responsible for significantly reduced breakdown field strengths observed for gate oxides in the MCT and IGBT devices. A failure mechanism based on lattice misfit stress and implantation damage below the amorphization threshold is proposed, which explains the observation that breakdown events occur exclusively at the very periphery of the implanted regions. This is in accordance with the scaling law that is found, exhibiting a logarithmic relationship between the breakdown strength of MOS capacitors and the perimeter length of p/sup +/ regions in the substrate. The substantial reduction in breakdown field strength was found to result in yield losses. By appropriate separate annealing of the p/sup +/-emitter, such weak spots in the gate oxide are not observed. With the use of BF/sub 2//sup +/ for the p/sup +/-emitter implantation it was possible to prevent yield losses and to reach intrinsic breakdown field strengths while still staying with the simplified device processing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This chapter focuses on commonly used high‐power semiconductor devices including silicon controlled rectifiers (SCRs), gate turn‐offs (GTOs), gate commutated thyristors (GCTs), and insulated gate bipolar transistors (IGBTs) for medium voltage (MV) drives. It discusses the static and dynamic voltage equalization techniques for series connected devices, and compares the performance of these devices. A new type of emerging power semiconductor devices is the silicon carbide (SiC), which is a compound semiconductor composed of silicon and carbon. The SiC power devices are able to operate at higher switching speed and higher temperature with lower switching and conduction losses in comparison to the silicon devices such as IGBTs. The static and dynamic voltage equalization techniques for the GCT devices can be equally applied to the IGBTs. In addition, an active overvoltage clamping scheme can be implemented to limit the collector‐emitter voltage during switching transients.

This paper introduces a new method of IGBT switching loss reduction on the system level, while leaving the PWM scheme completely unchanged. The switching loss reduction is achieved by designing an IGBT gate driver that dynamically sets the IGBT gate current depending on feedback signals from IGBT current, IGBT voltage, phase load current, and DC link voltage if it is not constant in the application. Factors influencing switching losses will be demonstrated for two types of output driver stages: one with discrete switching speed setting and one with continuously variable switching speed. Comparing to other gate driver types with or without feedback aimed at keeping constant dv/dt, di/dt, and overshoots of IGBT voltage and current, the proposed gate driver not only ensures the operation of an IGBT in the safe operating area (SOA), but also improves the SOA utilization density by tracking the programmed voltage and current limits using peak-detection circuitry while minimizing the switching losses. Adaptive feedback control algorithms have been developed and verified by simulations.

The increase of the switching speed in power semiconductors leads to converters with better efficiency and high power density. On the other hand, fast switching generates some consequences like overshoots and higher switching transient, which provoke electromagnetic interference (EMI). This paper proposes a new closed-loop gate driver to improve switching trajectory in insulated gate bipolar transistors (IGBTs) at the hard switching condition. The proposed closed-loop gate driver is based on an active gate voltage control method, which deals with emitter voltage (VEe) for controlling diC/dt and gets feedback from the output voltage (vCE) in order to control dvCE/dt. The sampled voltage signals modify the profile of the applied gate voltage (vgg). As a result, the desired gate driver (GD) improves the switching transients with minimum switching loss. The operation principle and implementation of the controller in the GD are thoroughly described. It can be observed that the new GD controls both dvCE/dt and diC/dt accurately independent of the variable parameters. The new control method is verified by experimental results. As a current issue, the known trade-off between switching losses and EMI is improved by this simple and effective control method.

This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV2 gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.

There is a continuous demand for improvements in the quality of switching power devices, such as higher switching frequency, higher withstand voltage capability, larger current-handling capability, and lower conduction losses. However, for single-conduction-mechanism devices (SCRs, GTOs, BJTs, FETs), possessing all these features is probably unrealizable for physical reasons. An attractive solution appears to be double-mechanism devices, in which the features of both a minority carrier device (BJT or SCR) and a majority carrier device (MOSFET) are embedded. Both IGBTs (insulated-gate bipolar transistors) and MCTs (MOS-controlled thyristors) belong to this family of double-mechanism devices and promise to have a major impact on converter circuit signs. The authors deal with the major features of these two devices, pointing out those that are most critical to the design of power converter topologies. In particular, the two devices have been tested both in a chopper and in two resonant link converter topologies, and the experimental results are reported. >

SUMMARYThis paper presents a gate driver with fast switching and low switching loss for silicon carbide‐metal oxide semiconductor field effect transistors. The proposed driver consists of a very simple gate boost circuit and a speed up circuit, and so is cost‐effective. Normally, conventional gate drive methods include a trade‐off between switching losses and noise. The proposed gate driver can reduce switching losses without increasing surge voltage as well as voltage and current fluctuations. The proposed gate driver is able to eliminate the trade‐offs in the switching characteristics.

The new smart high-voltage gate drivers, the IXBD4410 and the IXBD4411, were designed to drive and protect power MOS and insulated gate bipolar transistor (IGBT) devices and modules in a phase leg or a totem pole inverter output configuration. These gate drivers function reliably under extreme d nu /dt and di/dt noise environments, with the half bridge inverter output voltages limited only by the breakdown of the external discrete devices. The IXBD4410 provides a diagnostic fault output flag, reflecting the condition of not only the low side but the high side device in a half bridge application. The IXBD4410 family devices can be configured to detect operating overcurrents using a resistor in series with the power device source, or by using one of several desaturation sense circuits presented. If the drive current output of the IXBD4410 is not adequate, a simple circuit consisting of a pair of complementary bipolar transistors can be placed between the IXBD4410 family device and the power MOS, IGBT, or module.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Interleaved switching of parallel inverters has previously been proposed for efficiency/size improvements of grid connected three-phase inverters. This paper proposes a novel interleaving method which practically eliminates insulated gate bipolar transistor (IGBT) turn-on losses and drastically reduces diode reverse recovery losses. The reduction in switching losses are obtained by interleaving two parallel inverter branches so that only one branch conducts the load current at a time. By placing saturable inductors between the parallel branches, soft switching may be obtained, and thereby overall power module losses are reduced. The modulation strategy is suited for converters with doubly fed induction generators (DFIG) for wind turbines, but are not limited hereto. Improvement of switching performance are measured and operational efficiency improvements are calculated and verified in an operating inverter.

The authors present a gate control circuit for an MCT (MOS controlled thyristor) and study its switching characteristics. The response times and switching loss are accurately measured under different operating conditions. The authors also present a simple PSPICE circuit model for the MCT which can be used to analyze MCT power converters. The parameters of the model are determined from the manufacturer's specifications and some simple measurements. The complete circuit of a DC chopper was simulated using PSPICE, and the simulated responses are compared with the experimental responses. >