Implementation-Friendly Constraint for Adaptive Finite Impulse Response Filters for Equalization

This This paper describes the design and the testing of an adaptive FIR filter built on an FPGA using the Least Mean Squares (LMS) algorithm. The study compares different types of multipliers, such as the traditional array multiplier (conventional type), the Vedic multiplier, and the Binary Coded Decimal (BCD) multiplier, within a 3-tap FIR filter design. The multiplier unit has been the target for better architecture performance as it has a principal role in the finite impulse response (FIR) filter. Having been designed using Verilog, all conducted multiplier were tested to decide the best among them for the adaptive FIR filter. Testing the design was done in Quartus II and ModelSim software. Results illustrated that the BCD multiplier type was the most qualified through using only 12 registers and 151 logic elements compared to Array and Vedic multipliers. Obtained simulated results offers a maximum speed of 1282.05 MHz. Also, the performance of the design reflects an apparent error reducing of the tested signal with proper values compared to theoretically obtained results. Generally, the proposed FPGA based adaptive FIR system supports its effectiveness and reliability along with capability of high-speed operation.

This paper presents an acoustic noise cancelling technique using an inverse kepstrum system as an innovations-based whitening application for an adaptive finite impulse response (FIR) filter in beamforming structure. The inverse kepstrum method uses an innovations-whitened form from one acoustic path transfer function between a reference microphone sensor and a noise source so that the rear-end reference signal will then be a whitened sequence to a cascaded adaptive FIR filter in the beamforming structure. By using an inverse kepstrum filter as a whitening filter with the use of a delay filter, the cascaded adaptive FIR filter estimates only the numerator of the polynomial part from the ratio of overall combined transfer functions. The test results have shown that the adaptive FIR filter is more effective in beamforming structure than an adaptive noise cancelling (ANC) structure in terms of signal distortion in the desired signal and noise reduction in noise with nonminimum phase components. In addition, the inverse kepstrum method shows almost the same convergence level in estimate of noise statistics with the use of a smaller amount of adaptive FIR filter weights than the kepstrum method, hence it could provide better computational simplicity in processing. Furthermore, the rear-end inverse kepstrum method in beamforming structure has shown less signal distortion in the desired signal than the front-end kepstrum method and the front-end inverse kepstrum method in beamforming structure.

This paper presents analysis of nonminimum phase component on acoustic transfer function as unknown system when adaptive FIR (finite impulse response) filter is used for noise cancelling scheme. For the application in realistic reverberant environment, nonminimum phase component is analyzed in beamforming structure. From the analysis, it has been found that it provides a consistency in estimate by adaptive FIR filter between direct and its inverted transfer functions. Based on this, by applying minimum phase filter in front, it will be shown that rear-end adaptive FIR filter is only related with nonminimum phase term due to absorption of minimum phase term by front-end minimum phase filter in beamforming structure.

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity.

Nowadays, the communications and computations has been performed by Digital Finite Impulse Response (FIR) filter. FIR filter is predominantly used in DSP applications for efficient implementations. FIR filter is able to declare a firm linear phase frequency characteristic with any type of amplitude frequency characteristic in a DSP system. A reconfigurable FIR filter architecture has been implemented using Least Mean Square (LMS) algorithm in the proposed scheme. The proposed scheme achieves better performance when compared to an existing scheme. The proposed method has been implemented in ModelSim tool and efficiency has been calculated by using the device Virtex 6 Low Power in Xilinx ISE Design Suite 12.4.

PurposeTraditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.Design/methodology/approachRather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.FindingsAn ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.Originality/valueA software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

This paper proposes the least mean square (LMS) algorithm based versatile, vector, and fault tolerant adaptive finite impulse response (FIR) filter designs. Here, the M-taps versatile design is to perform the filter operation with the number of filter co-efficients varied from 2 to M. The M-taps vector design is to perform \(\lfloor \frac{M}{L}\rfloor \) numbers of L-taps filter operations in parallel, where \(M\ge L\). The fault tolerant M-taps filter is to perform the \((M-N)\)-taps fault free filter operation under the N numbers of faulty filter kernels, where \((M-N)\ge 2\). All the existing and proposed designs are implemented with 45 nm CMOS technology. The proposed 16-taps vector adaptive filter design achieves \(93\%\) of improvement in throughput as compared with the distributed arithmetic based design.

We describe the application of a genetic algorithm (GA) to the problem of parameter optimization for an adaptive finite impulse response (FIR) filter combining genetic algorithm (GA) and least mean square (LMS) algorithm. For system identification problem, LMS algorithm computes the filter coefficients and GA search the optimal step-size adaptively. Because step-size influences on the stability and performance, so it is necessary to apply method that can control it. The simulation results of the GA were compared to the traditional LMS algorithm. We obtained that genetic algorithm was clearly superior (in accuracy) in most cases.

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Digital filters play a central role in modern digital signal processing (DSP) systems. Finite impulse response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

SummaryThis work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns.

WITHDRAWN: An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

Costas loops are invariably designed in conjunction with an automatic gain control (AGC) loop for stabilizing performance. In such systems an inherent coupling between the AGC and Costas loops develops, complicating the standard phase referencing analysis. This coupling is further emphasized if the gain control amplifier introduces an AM/PM conversion, which causes power variations to enter the Costas loop as phase variations. In this paper the coupling effect between AGC and Costas loops is developed, leading to a pair of joint, interconnected dynamical tracking loops. Some degree of solution is attainable by assuming a first order AGC loop, and resorting to quasi-stationary analysis for evaluating the phase referencing generation. Results with and without AM/PM are presented, and illustrate how an improper AGC may in fact degrade the phase referencing from the expected performance.

Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic