Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCL

The NAS Parallel Benchmarks for evaluating C++ parallel programming frameworks on shared-memory architectures

Advances in deep neural networks have provided a significant improvement in accuracy and speed across a large range of Computer Vision (CV) applications. However, our ability to perform real-time CV on edge devices is severely restricted by their limited computing capabilities. In this paper we employ Vega, a parallel graph-based framework, to study the performance limitations of four heterogeneous edge-computing platforms, while running 12 popular deep learning CV applications. We expand the framework's capabilities, introducing two new performance enhancements: 1) an adaptive stage instance controller (ASI-C) that can improve performance by dynamically selecting the number of instances for a given stage of the pipeline; and 2) an adaptive input resolution controller (AIR-C) to improve responsiveness and enable real-time performance. These two solutions are integrated together to provide a robust real-time solution. Our experimental results show that ASI-C improves run-time performance by 1.4x on average across all heterogeneous platforms, achieving a maximum speedup of 4.3x while running face detection executed on a high-end edge device. We demonstrate that our integrated optimization framework improves performance of applications and is robust to changing execution patterns.

Optimization of data-parallel applications for modern HPC platforms requires partitioning the computations between the heterogeneous computing devices in proportion to their speed. Heterogeneous data partitioning algorithms are based on computation performance models of the executing platforms. Their implementation is not trivial as it requires: accurate and efficient benchmarking of computing devices, which may share resources and/or execute different codes; appropriate interpolation methods to predict performance; and advanced mathematical methods to solve the data partitioning problem. In this paper, we present FuPerMod, a software tool that addresses these implementation issues and automates the development of data partitioning code in data-parallel applications for heterogeneous HPC platforms.

With the emergence of inexpensive commercial off-the-shelf (COTS) parts, heterogeneous multi-processor HPC platforms have now become more affordable. However, the effort required in developing real-time applications that require high-performance and high input/output bandwidth for the HPC systems is still difficult. There are no software tools that allow an engineer to develop and field applications efficiently on the HPCs. This paper describes Honeywell's Multi-domain Embedded System Architect tool suite (MESA). The tool suite allows an engineer to rapidly develop an application on a COTS based heterogeneous HPC platform, effectively reducing the development time. To illustrate the cost benefit and the user friendliness of MESA, the mapping of the bistatic radar application on Honeywell's HPC will be presented.

Massively parallel architectures are mainly based on a parallel heterogeneous setup. They are composed by different computing devices that speed up specific code regions, named kernels. These kernels are usually executed offline in the corresponding devices. Porting applications to a specific heterogeneous platform is a costly task in terms of time and human resources. The key points in the porting process are the manual analysis of the source code and kernel detection. Each device of these heterogeneous platforms has their own restrictions, such as the memory allocation support. Kernels must be mapped with suitable computing devices. We introduced AKI as an automatic kernel identification and annotation tool that aims to identify potential kernels on C $$++$$ sequential applications. AKI identifies those kernels that can be offlined on heterogeneous computing devices. To annotate these kernels, REPARA C++ attributes have been defined. This annotation mechanism can aid future automatic source-to-source transformation tools to facilitate the work for parallel heterogeneous platforms. AKI has been evaluated over all benchmarks included in the NAS suite. The benchmark suite incorporates a big set of realistic high performance applications. The evaluation results demonstrate that AKI is a competitive solution for identifying and annotating parallel code fragments (aka kernels).

The recent emergence of new memory technologies and multi-tier memory architectures has disrupted the traditional view of memory as a single block of volatile storage with uniform performance. Several options for managing data on heterogeneous memory platforms now exist, but current approaches either rely on inflexible, and often inefficient, hardware-based caching, or they require expert knowledge and source code modification to utilize the different performance and capabilities within each memory tier. This paper introduces a new software-based framework to collect and apply memory management guidance for applications on heterogeneous memory platforms. The framework, together with new tools, combines a generic runtime API with automated program profiling and analysis to achieve data management that is both efficient and portable across multiple memory architectures.To validate this combined software approach, we deployed it on two real-world heterogeneous memory platforms: 1) an Intel® Cascade Lake platform with conventional DDR4 alongside nonvolatile Optane™ DC memory with large capacity, and 2) an Intel® Knights Landing platform high-bandwidth, but limited capacity, MCDRAM backed by DDR4 SDRAM. We tested our approach on these platforms using three scientific mini-applications (LULESH, AMG, and SNAP) as well as one scalable scientific application (QMCPACK) from the CORAL benchmark suite. The experiments show that portable application guidance has potential to improve performance significantly, especially on the Cascade Lake platform -- which achieved peak speedups of 22x and 7.8x over the default unguided software- and hardware-based management policies. Additionally, this work evaluates the impact of various factors on the effectiveness of memory usage guidance, including: the amount of capacity that is available in the high performance tier, the input that is used during program profiling, and whether the profiling was conducted on the same architecture or transferred from a machine with a different architecture.

In the past few years, with the rapid development of heterogeneous computing systems (HCS), the issue of energy consumption has attracted a great deal of attention. How to reduce energy consumption is currently a critical issue in designing HCS. In response to this challenge, many energy-aware scheduling algorithms have been developed primarily using the dynamic voltage-frequency scaling (DVFS) capability which has been incorporated into recent commodity processors. However, these techniques are unsatisfactory in minimizing both schedule length and energy consumption. Furthermore, most algorithms schedule tasks according to their average-case execution times and do not consider task execution times with probability distributions in the real-world. In realizing this, we study the problem of scheduling a bag-of-tasks (BoT) application, made of a collection of independent stochastic tasks with normal distributions of task execution times, on a heterogeneous platform with deadline and energy consumption budget constraints. We build execution time and energy consumption models for stochastic tasks on a single processor. We derive the expected value and variance of schedule length on HCS by Clark's equations. We formulate our stochastic task scheduling problem as a linear programming problem, in which we maximize the weighted probability of combined schedule length and energy consumption metric under deadline and energy consumption budget constraints. We propose a heuristic energy-aware stochastic task scheduling algorithm called ESTS to solve this problem. Our algorithm can achieve high scheduling performance for BoT applications with low time complexity $O(n(M+\log n))$ , where $n$ is the number of tasks and $M$ is the total number of processor frequencies. Our extensive simulations for performance evaluation based on randomly generated stochastic applications and real-world applications clearly demonstrate that our proposed heuristic algorithm can improve the weighted probability that both the deadline and the energy consumption budget constraints can be met, and has the capability of balancing between schedule length and energy consumption.

The number of processors is increasing, but the usefulness of parallel computation is not better leveraged due to the inflexibility of design and implementation for multiprocessor embedded system applications. A higher level abstraction (i.e., a parallel programming framework) can ease the programmers to define parallelism for tasks in an application but designers still face the complexity of mapping high-level requirements to the syntax and semantics of a parallel programming interface. Nevertheless, embedded system applications execute various periodic tasks that are carried out repeatedly within a certain time interval and these tasks may be able to run in parallel to utilize the system efficiently. Therefore, in this paper, we propose a parallel loop-based task construct approach to automate the design process of embedded system applications from AADL models for a parallel programming framework. To illustrate the applicability of our mechanism, we use a well-known parallel programming interface called OpenMP to demonstrate the automation process in mapping tasks over multiple processor cores. To ensure meeting high-level requirements of embedded system applications, we analyze the existing OpenMP scheduling mechanisms and propose a layer of adaptation. We show that our proposed adaptation layer facilitates a tighter execution time bound for time-sensitive tasks or a better throughput for tasks that require higher quality of service. Thus, the proposed design automation framework is applicable for a variety of applications with different quality of service (QoS) requirements preserved at the lower level.

The increasing popularity and usage of internet based services makes design of software system complex and their power unlimited in scale. These systems often involve heterogeneous environment and platforms. They continuously evolve in order to meet the changes in technology and business practices. Emergence of information system architecture based on disparate externally provided internet based services warrant incorporation of novel design primitives in the application design. Traditionally popular application design primitives includes separation, abstraction, compression, uniform composition, replication and resource sharing that has evolved and came to vogue based on past experience and expert practice. This work examines and evaluates approaches to incorporation of new and novel unit operations around which applications can be architected, designed and analyzed for the internet computing and big data era. Incidentally it is found that portions of agent technology provides several unit operations such as migration of code and speech-act based responsibility delegation/application composition as application architectural primitives. This work determines extensions to Web Services-Business Process Execution Language (WS-BPEL) programming framework--called as ACtive Internet Application Framework (ACIAF) and is suited for incorporation of novel unit operations such as migration of code and speech-act based component orchestration/application composition to enable construction of next generation information systems. An analysis of merits and demerits of using WS-BPEL technology to realize ACIAF is also carried out here. Code mobility feature of ACIAF is demonstrated using a use case while loosely coupled application design using ACIAF is theoretically discussed. Formal analyzability of mobility behavior of ACIAF application is highlighted based on its conformance to Petri-net formalism. Further formal logical analyzability/interpolatability of individual actions performed by collaborating ACIAF applications is also highlighted. It is argued here that ACIAF shall provide necessary foundation, guidance and motivation for further detailed technical work on several ideas presented to realize next generation information systems. This work firmly establishes extension to WS-BPEL platform as a most viable approach to realize novel architectural primitives to the design and implementation of next generation information systems.

As the scale of China’s interconnected power grid continues to expand, traditional serial computing methods are no longer sufficient for the rapid analysis and computation of electrical networks with tens of thousands of nodes due to their small scale and low efficiency. To enhance the capability of online grid analysis, this paper introduces an accelerating batched power flow calculation method based on a heterogeneous CPU-GPU platform. This method, based on the fast decoupled method, combined with the tremendous parallel computing capability of GPUs with the multi-threaded parallel processing of CPUs, efficiently resolves the exceeding bus type conversion issues in GPU-batched power flow calculation and improves the accuracy of the power flow calculations. Then, a binary-based power flow data exchange format was introduced, which utilizes a single binary file for data exchange. This format significantly minimizes I/O time overhead and reduces file size, further enhancing the method’s efficiency. Case studies on real-world power grids demonstrate its high accuracy and reliability. Compared to the traditional single-threaded power flow calculation method, this method dramatically reduces time consumption in batch power flow calculations. It proves the significant advantages of dealing with large-scale power flow calculations.

The healthcare industry has been using data and technology driven innovation for a long time now with Evidence Based Medicine (EBM) being at the helm. Effectively using technology is vital towards successful data management in healthcare. A convenient approach that can collect, store, evaluate, and analyze health data will be beneficial to all the stakeholders in the healthcare delivery chain. With the advancement, clubbed with the availability and affordability of technology, it has become an effective tool for providing the right- care backed with accurate, consolidated evidence. Such approach not only helps in improving the quality of care, it also helps in early detection of diseases and effective treatment, Big Data is providing the necessary data management tools for the same. A simple Extract-Transform-Load (ETL) procedure using Hadoop can be used. As Big data analyses large amounts of data to uncover hidden patterns, correlations and other insights, its role in making the right, predictive decisions for quality care of the patients and better health planning is possible. Big data technologies such as Hadoop bring significant cost advantages when it comes to storing large amounts of data and combined with the speed of Hadoop and in-memory analytics, with the ability to analyze new sources of data, we are able to analyze information instantly – and make decisions which is very essential in the healthcare provider segment. Hadoop does not only store, but also process any and many file data: big or small, can be plain text files or binary files like images and even multiple different version of some particular data format across different time periods. It consists of three core components: a distributed file system, a parallel programming framework, and a resource/job management system. In healthcare, patient records, health plans, insurance information and other types of information is extremely difficult to manage – but, this very data is full of key insights, the need is for an effective data management and analytics that can be pragmatic. By analyzing large amounts of information – both structured and unstructured – rapidly, health care providers can provide lifesaving diagnoses. Keywords: Big Data, EBM, ETL, Hadoop

The Standard Template Adaptive Parallel Library ( stapl ) is a parallel programming framework that extends C++ and stl with support for parallelism. stapl provides a collection of parallel data structures ( pContainers ) and algorithms ( pAlgorithms ) and a generic methodology for extending them to provide customized functionality. stapl pContainers are thread-safe, concurrent objects, i.e., shared objects that provide parallel methods that can be invoked concurrently. They also provide appropriate interfaces that can be used by generic pAlgorithms . In this work, we present the design and implementation of the stapl associative pContainers : pMap , pSet , pMultiMap , pMultiSet , pHashMap , and pHashSet . These containers provide optimal insert, search, and delete operations for a distributed collection of elements based on keys. Their methods include counterparts of the methods provided by the stl associative containers, and also some asynchronous (non-blocking) variants that can provide improved performance in parallel. We evaluate the performance of the stapl associative pContainers on an IBM Power5 cluster, an IBM Power3 cluster, and on a linux-based Opteron cluster, and show that the new pContainer asynchronous methods, generic pAlgorithms (e.g., pfind ) and a sort application based on associative pContainers , all provide good scalability on more than 103processors.

In the era of technology, the amount of textual data has dramatically grown and increased. It is also getting to be more complex in its nature every day. The ability to manage, analyze, summarize, and understand this data remains a challenging task that requires new techniques to deal with automatically organizing, searching, indexing, and browsing large collections of documents. Text classification is one of text mining areas, which is the process of classifying the text into predefined classes or topics. We developed a tool for Arabic text classification using parallel programming framework. The tool is called Parallel Arabic Text Classifier (PATC). It analyzes a labeled corpus of Arabic text that is input by the user and subsequently builds a text classifier. PATC consists of three major stages; (1) Preprocessing: PATC will normalize and stem the Arabic corpus before using it to train the classifier, (2) Training or Building the Classifier: The classifier will be trained with a user-uploaded, annotated Arabic corpus, and (3) Testing or Classifying: this stage will predict the class of a new document based on the trained classifier. This classifier is built using an approach that associates each label with frequent words using MapReduce distributed programming model. The classifier was evaluated using an Arabic corpus. The accuracy of the classification was around 80% using single-label measures, while it was in the high 90s% using multi-label measures.

Parallel programming can be extremely challenging. Programming models have been proposed to simplify this task, but wide acceptance of these remains elusive for many reasons, including the demand for greater accessibility and productivity. In this paper, we introduce a parallel programming model and framework called CharmPy, based on the Python language. CharmPy builds on Charm++, and runs on top of its C++ runtime. It presents several unique features in the form of a simplified model and API, increased flexibility, and the ability to write everything in Python. CharmPy is a high-level model based on the paradigm of distributed migratable objects. It retains the benefits of the Charm++ runtime, including dynamic load balancing, asynchronous execution model with automatic overlap of communication and computation, high performance, and scalability from laptops to supercomputers. By being Python-based, CharmPy also benefits from modern language features, access to popular scientific computing and data science software, and interoperability with existing technologies like C, Fortran and OpenMP. To illustrate the simplicity of the model, we will show how to implement a distributed parallel map function based on the Master-Worker pattern using CharmPy, with support for asynchronous concurrent jobs. We also present performance results running stencil code and molecular dynamics mini-apps fully written in Python, on Blue Waters and Cori supercomputers. For stencil3d, we show performance similar to an equivalent MPI-based program, and significantly improved performance for imbalanced computations. Using Numba to JIT-compile the critical parts of the code, we show performance for both mini-apps similar to the equivalent C++ code.

Statistical energy optimization on voltage–frequency island based MPSoCs in the presence of process variations