Implementation of Data Acquisition and Processing IP core for Digital Protective Relay

The modus operandi of the upfront intellectual property (IP) licensing model is impractical for the developers of small to medium volume of field-programmable gate array (FPGA)-based applications. The FPGA IP market is in dire need for a more competitive and secure IP licensing scheme to flourish. In this paper, a pragmatic security protocol that could support the licensing of IP cores on a per-device basis without the need for a contractual agreement of an external trusted third party, large bandwidth, and complicated flow of communications is proposed. Besides assuring that the incentives of all stakeholders involved in the FPGA IP core trading are not scarified if not enhanced, the proposed protocol guarantees total secrecy and integrity of licensed IP cores based on available primitives of contemporary SRAM-based FPGA devices. It also prohibits the implementation of protected IP cores on unscreened excess devices and counterfeit chips sold in the gray market. The adoption of IP fingerprinting further deters the IP licensees from abusing the IP cores. Using the self-reconfiguration feature of FPGAs today, the resources consumed by the control module used for the implementation of protected IP cores on the authorized device are temporary and marginal.

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.

Modern Systems-on-a-Chip (SoC) are constructed by composition of IP (Intellectual Property) Cores with the communication between these IP Cores being governed by well described interaction protocols. However, there is a disconnect between the machine readable specification of these protocols and the verification of their implementation in known hardware description languages. Although tools can be written to address such a separation of concerns, such tooling is often hand written and used to check hardware designs a posteriori. We have developed a dependent type-system and proof-of-concept modelling language to reason about the physical structure of hardware interfaces respective to user provided descriptions. Our type-system provides correct-by-construction guarantees that the interfaces on an IP Core will be well-typed if they adhere to a specified standard.

This paper proposes an improved procedure to watermark soft Intellectual Property (IP) Cores at the Register Transfer Level (RTL) using Genetic Algorithms (GA). In order to merge the watermark signature and the IP Core's behavioral description, both are translated into Finite State Machines (FSM). The resulting FSM contains the watermarked IP Core maintaining its original functionality without disruption. However, a set of hanging states (a group of states not deeply embedded) has been observed and if any of these is deleted, the watermark could be removed and possibly the original IP Core functionality would not be disrupted, allowing for copyright infringements. Thus, a reduction procedure is applied to the watermarked design to reduce the number of hanging states, which to the best of the authors' knowledge has not been developed. Both FSM merging and reduction are NP-Complete problems. In this study, an improved objective function is proposed to accurately model the FSM reduction problem while applying GAs as optimization techniques at both stages. Empirical results show a significant improvement in terms of the number of final hanging states and watermark embedding strength as regards previous reported approaches.

Back-end-of-the-line (BEOL) interconnect technology is undergoing a rapid transformation as a result of the projected impact on IC performance at decreasing minimum feature sizes. As a result, design complexity is becoming the gating item in leading edge IC products, leading to increasing design reuse of IC functional building blocks (i.e. macrocells and intellectual property (IP) cores), particularly for advanced application specific ICs (ASICs) and system-on-a-chip (SOC) implementations. Virtual Design Environment (VDE) software developed for complex printed circuit boards will expand to the chip level as SOC implementations (and advanced ASICs) incorporate increasing use of IP cores and increasingly complex wiring designs. IC manufacturing operations will become increasingly involved in providing and licensing IP cores in support of this evolving design methodology.

The increasing gap between design productivity and chip complexity, and emerging systems-on-a-chip (SoC) have led to the wide utilization of reusable intellectual property (IP) cores. Educators' responsibility is to provide future generations of SoC architects with knowledge necessary for successful design and use of IP cores, and to offer them a system perspective including both hardware and software. One such proposal is to design an accelerometer IP core for advanced control applications such as robust motion control, servomotor or robotic applications. There are a lot of strong demands on motion control systems, with reasonable resolution and accuracy. The performance of such motion control systems can be greatly enhanced by including some form of velocity or acceleration feedback. An accurate and rapid velocity measurement is vital for high-performance acceleration control. The functionality of the system core is coded in Verilog HDL, mapped onto architecture, simulated, synthesized and implemented on FPGA and tested. The performance evaluation and validation of the developed core can also be done by comparison with a software model realized using Matlab Simulink. The velocity estimates of RTL model can be further improved by considering some factors affecting accuracy, resolution and range of velocity measurements. This validated velocity signals are used to compute the acceleration of the moving object using simple differentiation technique without accumulated quantization errors.

This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.

In this paper, we propose a hierarchical automatic test pattern generation (ATPG) framework that can generate custom tests for full-scan systems-on-chip (SOCs) containing intellectual property (IP) cores without revealing much IP. The proposed ATPG is shown to be correct and complete and its average and worst case complexities are shown to be comparable with those of classical ATPG. The proposed ATPG reduces DFT overheads and test application costs. It also enables utilization of a range of test methodologies at the SOC level.

In the modern electronic era, the increased usability and acceptability of reusable intellectual property (IP) cores induce the necessity to secure them from various hardware security threats and attacks. This chapter presents a taxonomy of hardware security methodologies for IP cores and a detailed design flow of hardware integrated circuits (ICs) along with vulnerability points where potential attacks/threats are possible. Trustworthy and untrustworthy regimes in the design flow have also been highlighted in the discussion. Further, a discussion of detective and preventive control-based hardware security approaches used for hardware IP cores have also been presented, including an analysis of prominent structural obfuscation, logic locking (logic encryption), and IP core protection (IPP) techniques. Each approach has been lucidly explained in terms of its threat model, algorithm, and security analysis. Finally, a security comparison of hardware IP obfuscation approaches in terms of strength of obfuscation security metric as well as security comparison of IPP approaches in terms of probability of coincidence security metric have also been introduced.

With the development of research on IEEE Std1500, IP (Intellectual Property) cores compatible with IEEE Std1500 are more and more. IEEE Std1500 provides wrapper architecture and TAM (Test Access Mechanism) for DFT (Design for Testability) of IP cores. So, the design of TAM becomes an important part of DFT for IP cores. Familiar TAM is introduced first, and then according to the characters of wrapper architecture, a TAM design based on bus is put forward. At last, TAM controller design for configurations of TAM is provided.

In the July 2016 issue of IEEE Consumer Electronics Magazine, the Hardware Matters column discussed intellectual property (IP) cores, and several articles have been presented that discoursed on topics ranging from the evolution of IP core design, to the protection of IP cores, to high-level perspectives on IP cores. In all of these articles, the resiliency aspect of IP core design has not been touched upon. In this issue?s column, I intend to present a deep cognizance to IEEE Consumer Electronics Magazine readers regarding the resiliency aspects of IP cores against terrestrial transient faults, which are seen as a major contributing factor to the eventual malfunctioning of integrated circuits (ICs).

With the increasing complexity and chip scale of SoC, the test problem is becoming more difficult and important. Adding DFT (design for testability) in SoC design period has become the main method for solving the test problem. Based on analyzing some common DFT structures such as Fscan-Bscan, Fscan-Tbus, and the standard for embedded core test (SECT) IEEE P1500, a system-level mixed DFT-TAM (test access mechanism) structure has been presented in this paper. In this structure, different DFT methods are applied in different characteristic IP (intellectual property) cores to pursue the reasonable testing cost, then, a more flexible TAM is built in the system level for achieving every IP core test and testing the connection faults between two IP cores. By some experiments with the programmable video add data (VAD) SoC introduced in this paper, the higher fault coverage and lower test cost could be gotten

In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput.

This paper deals with Intellectual Property (IP) core design for dynamic task scheduling to support Out-of-Order (OoO) execution in Multiprocessor System-on-Chip (MPSoC) environment. MPSoC is one of the most promising future processor architecture. But such systems have to face challenges in the context of OoO execution during dynamic scheduling due to data dependencies like Read-after-Write (RAW), Write-after-Write (WAW) and Write-after-Read (WAR). Due to these dependencies stalling problem occur during OoO execution. In order to solve this stalling problem and achieve task level parallelism (TLP), Scoreboarding algorithm with register renaming technique is designed. As these dependencies impose challenging constraints on the direct use of techniques like OoO execution, register renaming and dynamic scheduling, a synthesizable IP core is designed. The simulation results show that the design can analyze all the task dependencies during run-time and resolves them at TLP. This algorithm is able to resolve 100% RAW, WAW and WAR hazards which are not solvable at instruction level parallelism (ILP).

For different engineering applications, neural networks vary in scale, topology, transfer functions and learning algorithms. A reconfigurable approach for neural hardware implementation is proposed: neural algorithms are decomposed into several basic computations executed by reconfigurable processing units (RPU), which are designed carefully as IP (Intellectual Properties) cores and saved in core library; all the RPUs are interconnected in regular systolic arrays; when neural networks changed, new hardware can be reconfigured using FPGA and IP cores. Some key issues in implementation are discussed and a platform is developed for this approach. Comparisons with other implementations show that this approach has higher performances also with the flexible features.