Implementation of the Phase II Compiler for the ARM7TDMI-S Dual-Core Microprocessor

In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

The paper presents a FIFO queue based, scalable spin lock (FSSL) that: (1) uses only one atomic swap operation; (2) is scalable as it requires a constant amount of communication; (3) runs without a coherent cache support; and (4) provides a timing guarantee suitable for real time applications. The algorithm is optimal in the number of atomic operations required to solve the scalable mutual exclusion problem in NUMA architectures, improving on T. Craig's (1993) spin lock that uses four atomic swap operations. The FSSL algorithm minimizes the number of atomic operations by replacing them with non atomic read and write operations, and takes good advantage of recent multiprocessors where non atomic memory operations are much more optimized than atomic operations. The algorithm runs correctly in various weakly consistent memories, providing a potentially significant speedup over algorithms with more atomic operations.

Fast analysis of molecular dynamics trajectories with graphics processing units—Radial distribution function histogramming

The key to optimizing software is the correct choice, order as well parameters of optimizations-transformations, which has remained an open problem in compilation research for decades for various reasons. First, most of the compilation subproblems-transformations are interdependent and thus addressing them separately is not effective. Second, it is very hard to couple the transformation parameters to the processor architecture (e.g., cache size and associativity) and algorithm characteristics (e.g. data reuse); therefore compiler designers and researchers either do not take them into account at all or do it partly. Third, the search space (all different transformation parameters) is very large and thus searching is impractical. In this paper, the above problems are addressed for data dominant affine loop kernels, delivering significant contributions. A novel methodology is presented that takes as input the underlying architecture details and algorithm characteristics and outputs the near-optimum parameters of six code optimizations in terms of either L1,L2,DDR accesses, execution time or energy consumption. The proposed methodology has been evaluated to both embedded and general purpose processors and for 6 well known algorithms, achieving high speedup as well energy consumption gain values over gcc compiler, hand written optimized code and Polly.

The Internet of Things (IoT) is rapidly enabling applications in many different fields by embedding itself into the physical world. Many potential IoT devices require some level of machine learning or cognitive capability to be truly effective, but the high computational complexity of cognitive algorithms makes them unsuitable for low-power IoT processors. To understand the design challenges of cognitive IoT devices, the authors study a cognitive drone application in a design space called Flying IoT. They find that the computing capability provided by typical drone processors falls far short of satisfying the real-time performance requirements of their application. To improve their processor’s performance on the edge while maintaining its low power consumption and small form factor, the authors propose a sensor-cloud architecture in which data collection is done at the edge and data processing is offloaded to the cloud. Their sensor-cloud architecture can process complex convolution neural network models nearly in real time with software optimizations such as downsampling and compression, while consuming less power than state-of-the art embedded processors such as the Jetson TX1.

Memory is a fundamental resource of the SAP HANA database. Understanding how the SAP HANA database requests, uses, and manages this resource is crucial to the understanding of SAP HANA. As Data is growing rapidly and these data is stored in memory to process. Increasing DB size is directly proportional to its memory consumed. SAP HANA provides a variety of memory usage indicators that allow for monitoring, tracking, and alerting. The most important indicators are used memory and peak used memory. Memory needs to be optimized, otherwise increasing Data size can?t be accommodated by existing memory. Since SAP HANA contains its own memory manager and memory pool, external indicators such as the size of resident memory at host level and the size of virtual and resident memory at process level can be misleading when you are estimating the real memory requirements of an SAP HANA deployment. SAP HANA integrates data from multiple areas within an organization, for example: Traditional business documents - including contracts and spreadsheets. UX/UI (User Experience/User Interface) - including website forms, emails and other customer interactions Mobile - information from the mobile devices of customers and your workforce. IoT (Internet of Things) - data from the many sensors that run in every aspect of a business, from warehouses and trucks to stores and offices. The SAP HANA system not only integrates all of this data; it can also apply machine learning and AI to analyze it instantly and deeply, accelerating real-time decision-making by providing key insights into a company?s operations.

The ARM processor is a dual width ISA processor that provides a 16-bit Thumb instruction set in addition to the 32-bit ARM instruction set. The compromises made in designing the Thumb instruction set leads to significantly increased instruction counts. This increase is in part due to the fact that only half of the register file is visible to most instructions in Thumb code. In this paper we address this inefficiency by providing a new instruction, the SetMask instruction, using which the compiler can change the visible subset of registers at any program point. Thus, through the use of this instruction the compiler can make use of all registers in all instructions. We present compiler techniques for allocating invisible registers and introducing SetMask instructions in a manner that the number of introduced instructions is minimized so that the increase in code size is insignificant. We implement this new instruction using the dynamic instruction coalescing framework which enables the SetMask instruction to have zero execution time cost. Our techniques eliminated 11.7% of MOV instructions from Thumb code while causing negligible code size increase.

This paper summarizes a project on the implementation of the ARM9TDM, a 32-bit RISC processor based on the ARM9TDMI. This core is the successor to the ARM7TDMI-S which is used for embedded applications requiring low power, small chip area, and high processing speed. The main features of the ARM9TDM are its use of a 5-stage pipelined datapath and a Harvard architecture that has separate data and instruction interfaces. It supports the ARMv4T instruction set architecture (ISA) that uses both the 32-bit ARM instructions and 16-bit Thumb instructions. It includes a high-speed multiplier and debug capabilities using JTAG boundary scan test interface. It does not include an EmbeddedICE-RT module. The project was coded using the Verilog Hardware Description Language and was simulated using Synopsys VCS. The verified code was synthesized in 0.25-micrometer standard cells using Synopsys Design Vision. The layout generated by Synopsys Astro was characterized as having a maximum operating frequency of 34.13 MHz, an average power consumption of 16 mW and a chip size of 1.5335 sq. mm.

Fault injection attacks (FIA), which cause information leakage by injecting intentional faults into the data or operations of devices, are one of the most powerful methods compromising the security of confidential data stored on these devices. Previous studies related to FIA on software report that attackers can skip instructions running on many kinds of devices through many means of fault injection. Most existing anti-FIA countermeasures on software are designed to secure against instruction skip (IS). On the other hand, recent studies report that attackers can use laser fault injection to manipulate instructions running on devices as they want. Although the previous studies show that instruction manipulation (IM) can attack the existing countermeasures against IS, no effective countermeasures against IM have been proposed yet to the best of our knowledge. In this paper, we define an attacker's model under the assumption that the attacker injects IM using a single-spot laser, and propose a coding method to verify data integrity secure against the assumed IM model in ARM 16-bit Thumb instruction set.

The paper describes a method for estimation and optimization of memory size in low power embedded systems. This approach can be treated as a pathfinder to efficiently optimize the memory module, in turn optimizing the design time. It can be even employed for high level memory exploration applications while successfully meeting the performance - cost design metrics of the system. The paper concludes with an implementation example of a Speech Recognition module, showing an effective reduction in the memory requirement of the system after memory optimization. Depending upon the results, even algorithm based optimization can be done with an aim of further reducing the memory size.

In this study two neural networks were implemented in order to emulate a retrieval model and to estimate the sulphur dioxide (SO 2 ) columnar content and plume height from volcanic eruption. ANNs were trained using all IASI channels in TIR as inputs, and the corresponding values of SO 2 content and height of plume obtained using the Oxford SO 2 retrievals as target outputs. The retrieval is demonstrated for the eruption of the Eyjafjallajokull volcano (Iceland) occured in 2010 and to three IASI images of the Grimsvotn volcanic eruption that occurred in May 2011, in order to evaluate the networks for a different eruption. The results of validation, both for Eyjafjallajokull and Grimsvotn independent datasets, provided RMSE values between neural network outputs and targets lower than 20 DU for SO 2 total column and 200 mb for plume height, therefore demonstrating the feasibility to estimate SO 2 values using a neural network approach, and its importance in near real time monitoring activities, owing to its fast application. Concerning the validation carried out with neural networks on images from the Grimsvotn eruption, the RMSE of the outputs remained lower than the Standard Deviation (STD) of targets, and the neural network underestimated retrieval only where target outputs showed different statistics than those used during the training phase.

Creating a biometric verification system in an energy and area constrained embedded environment is a challenging problem. Our paper describes a secure and efficient embedded fingerprint verification system for the "ThumbPod" embedded device, in which a complete real-time fingerprint recognition module, including both the minutiae extraction and the matching, works on a 50 MHz LEON-2 processor. As a result of the proposed SW/HW accelerations and memory optimizations, we achieve 65% reduction on the execution time and 67% reduction on the memory size against the reference implementation.

Boolean Satisfiability (SAT) is a classical NP-complete problem with both theoretical and practical interests. This paper presents our work in developing an application-specific processor for SAT based on a commercial configurable processor core. We customize the processor configuration and design new instruction extensions based on the data structure and atomic operations used in SAT. The customized processor has achieved around 24 /spl times/ speedup at a very low hardware cost. The small size of the processor makes it possible to integrate multiple processors and other customized logic into a single chip for an application-specific multiprocessor solution for SAT. Our work shows the strength of application-specific processing in accelerating applications with complex control and dynamic data structures - an area that has traditionally not been targeted by application-specific processing. It also demonstrates that configurable processor cores can be used to cut the development time and cost for designing and building such application-specific processors.

In HPC systems, the increasing need for a higher level of concurrency has led to packing more cores within a single chip. However, since multiple processes share memory space, the frequent access to resources in critical sections where only atomic operation has to be executed can result in poor performance. In this paper, we focus on reducing lock contention on the memory management system of an HPC manycore architecture. One of the critical sections causing severe lock contention in the I/O path is in the page management system, which uses multiple Least Recently Used (LRU) lists with a single lock instance. To solve this problem, we propose a Finer-LRU scheme, which optimizes the page reclamation process by splitting LRU lists into multiple sub-lists, each having its own lock instance. Our evaluation result shows that the Finer-LRU scheme can improve sequential write throughput by 57.03% and reduce latency by 98.94% compared to the baseline Linux kernel version 5.2.8 in the Intel Knights Landing (KNL) architecture.

Microblogging services have become among the most popular services on the web in the last few years. This led to significant increase in data size, speed, and applications. This paper presents Venus ; a system that supports real-time spatial queries on microblogs. Venus supports its queries on a spatial boundary $R$ and a temporal boundary $T$ , from which only the top- $k$ microblogs are returned in the query answer based on a spatio-temporal ranking function. Supporting such queries requires Venus to digest hundreds of millions of real-time microblogs in main-memory with high rates, yet, it provides low query responses and efficient memory utilization. To this end, Venus employs: (1) an efficient in-memory spatio-temporal index that digests high rates of incoming microblogs in real time, (2) a scalable query processor that prune the search space, $R$ and $T$ , effectively to provide low query latency on millions of items in real time, and (3) a group of memory optimization techniques that provide system administrators with different options to save significant memory resources while keeping the query accuracy almost perfect. Venus memory optimization techniques make use of the local arrival rates of microblogs to smartly shed microblogs that are old enough not to contribute to any query answer. In addition, Venus can adaptively, in real time, adjust its load shedding based on both the spatial distribution and the parameters of incoming query loads. All Venus components can accommodate different spatial and temporal ranking functions that are able to capture the importance of each dimension differently depending on the applications requirements. Extensive experimental results based on real Twitter data and actual locations of Bing search queries show that Venus supports high arrival rates of up to 64 K microblogs/second and average query latency of 4 msec.