Implementing fault injection and tolerance mechanisms in multiprocessor systems

Lightweight block ciphers are proposed for Internet of Things (IoT) edge devices to ensure secure data transmission with limited resources. However, past research has been designed on ideal channel models, disregarding the possibility of ciphertext errors caused by channel interference during actual transmission. This omission poses difficulties in ensuring the reliability of the ciphertext, especially in the Internet of Medical Things (IoMT) where resources are limited and data accuracy requirements are high. Designing a highly secure and reliable lightweight block cipher for such situations is one of the most challenging tasks. Hence, we propose a lightweight block cipher ECLBC with error detection and correction mechanisms. For security, ECLBC not only achieves a certain security level in fewer rounds but also achieves a mode transition within AND-Rotation-XOR (AND-RX) lightweight block ciphers. This transition involves a shift from the Feistel to the Substitution-Permutation Network (SPN) and from half-round key XOR to full-round key XOR. For reliability, ECLBC supports detecting and correcting erroneous ciphertext due to channel interference. Given the resource-constrained nature of IoMT devices, we implement the detection and correction mechanism of ECLBC based on the linear block code. Finally, various classical cryptography methods are employed to analyze the performance and security of the ECLBC.

Aiming at the difficulty of developing fault-tolerant and error-correcting mechanism in the reform and innovation, a new system of fault-tolerant and error-correcting mechanism in the field of information technology is proposed. Through the use of the systematic concept of reform and innovation, responsibility and achievements to promote the work of fault-tolerant and corrective mechanism into the working system, fault-tolerant and corrective pre-inspection information database, Error-tolerant and corrective procedures, error-tolerant cases, legal accounting information database and relevant departments, personnel to establish a fault-tolerant and corrective pre-inspection information database. The construction of this information system is helpful to improve the scientificity, systematicness, standardization and maneuverability of faulttolerance and correction work. It can lighten the ideological burden of cadres in exploiting and innovating work, and encourage cadres to take active actions and take actions, providing a new implementation path for fault-tolerance and correction work.

With technology scaling and complexity, better error detection and correction mechanisms within chips and systems are becoming increasingly important in order to provide sufficient protection against both soft and hard errors. Verifying the correctness of error detection circuits and ensuring they provide enough design coverage is a hard problem which usually involves substantial amount of manual work. This problem is even more challenging in the presence of different design methodologies, such as with the inclusion of third party IP blocks where functional descriptions of logic designs may not be available. This paper addresses the problem by proposing a completely automated RTL-based verification flow for error detection and correction circuits. Several related challenges are solved: first, that of identification of potential error detection circuits in logic designs where no functional description or methodology hints are given. Second, identification of structures of the latches that are potentially protected by such error detection circuits. Third, using formal verification for ensuring that the implemented circuits for resiliency indeed detect all single bit errors in the latches they are intended to cover. The approach is described with parity detection as an example, although it is extensible to other coding methods such as ECC and state orthogonality checking. Novel algorithms are given and results on industrial designs are presented.

In railways, if all the systems work synchronously and accurately then only security can be ensured. To avoid manual errors, we are hereby proposing a machine-to-machine communication network which will connect all critical machinery and subsystems. It will be a data aggregation and decision-making system during the railway operations. Whole critical machinery will be having their local error detection and correction mechanisms through sensors and transducers. They also have the proposed communication capability with the sink. All threats will be collected at a common node outside the train at a global sink which forwards the train required information for next 10-km propagation. A risk score is calculated which when higher than threshold then the train is signaled to stop immediately. All the threats have their priority score. Collected threats’ priority score is added to get final risk score. This is first ever implementation of machine-to-machine network for railway security. The implementation of work is done using MATLAB v14 which is used to simulate the proposed algorithm. The simulation results are compared with the previous approaches on the basis of average transmission time. Priority score-based analysis also is done in the simulation.

Approximate computing permits compromise on the accuracy of output of computational circuits to reduce the area of these circuits and lessen their power consumption. However, the acceptability of inexact output is an application specific phenomenon. In this paper, we particularly address the case of multiplier design such that features of accuracy and low area/power are equally sought, by proposing CMOS/Pass Transistor Logic (PTL) based approximate multiplier (MCPAM). MCPAM is a transistor level 2 by 2 novel approximate multiplier with minimum error distance and compact architecture. In case of applications with exact output requirements, MCPAM can be configured for accuracy through a proposed low-cost error detection and correction mechanism. The novelty of the method lies in the design of approximate multiplier that is to use static CMOS style and PTL logic together for low area/power design implementation. Experimental results and comparative analysis using 45nm demonstrate 60% to 83.6% and 71.3% improvement in power and area, respectively, as compared with previously proposed approximate multiplier. When MCPAM is used in conjunction with its error detection and correction unit, up to 37.4% and 17.3% reduction in area and power consumption, respectively, is observed as compared with previously proposed approximate multiplier employing error correction.

Quantum error correction plays a vital role in the Quantum information process. Nowadays, the research has been increased in quantum technology and is being applied in various applications like secure communications, finance, machine learning, drug analysis and etc. But the quantum information process is difficult compared to the classical due to the challenges in quantum technology like no-cloning theorem, decoherence, and the difficulty in quantum states measurement. Thus the error rate is high and it is not possible to build a quantum computer without an error detection and correction mechanism. In this paper, we are discussing various error correction methods and proposing a novel encoding method for quantum error correction.

Manufacturing and environmental variability lead to timing errors in computing systems that are typically corrected by error detection and correction mechanisms at the circuit level. The cost and speed of recovery can be improved by memoization-based optimization methods that exploit spatial or temporal parallelisms in suitable computing fabrics such as general-purpose graphics processing units (GPGPUs). We propose here a temporal memoization technique for use in floating-point units (FPUs) in GPGPUs that uses value locality inside data-parallel programs. The technique recalls (memorizes) the context of error-free execution of an instruction on a FPU. To enable scalable and independent recovery, a single-cycle lookup table (LUT) is tightly coupled to every FPU to maintain contexts of recent error-free executions. The LUT reuses these memorized contexts to exactly, or approximately, correct errant FP instructions based on application needs. In real-world applications, the temporal memoization technique achieves an average energy saving of 8%-28% for a wide range of timing error rates (0%-4%) and outperforms recent advances in resilient architectures. This technique also enhances robustness in the voltage overscaling regime and achieves relative average energy saving of 66 % with 11% voltage overscaling.

Speech production involves the careful orchestration of sophisticated systems, yet overt speech errors rarely occur under naturalistic conditions. The present functional magnetic resonance imaging study sought neural evidence for internal error detection and correction by leveraging a tongue twister paradigm that induces the potential for speech errors while excluding any overt errors from analysis. Previous work using the same paradigm in the context of silently articulated and imagined speech production tasks has demonstrated forward predictive signals in auditory cortex during speech and presented suggestive evidence of internal error correction in left posterior middle temporal gyrus (pMTG) on the basis that this area tended toward showing a stronger response when potential speech errors are biased toward nonwords compared to words (Okada et al., 2018). The present study built on this prior work by attempting to replicate the forward prediction and lexicality effects in nearly twice as many participants but introduced novel stimuli designed to further tax internal error correction and detection mechanisms by biasing speech errors toward taboo words. The forward prediction effect was replicated. While no evidence was found for a significant difference in brain response as a function of lexical status of the potential speech error, biasing potential errors toward taboo words elicited significantly greater response in left pMTG than biasing errors toward (neutral) words. Other brain areas showed preferential response for taboo words as well but responded below baseline and were less likely to reflect language processing as indicated by a decoding analysis, implicating left pMTG in internal error correction.

To evaluate the characteristics of commercial memory devices, Japan Aerospace Exploration Agency (JAXA) launched a solid state recorder (SSR) on the mission demonstration test satellite-1 (MDS-1 or Tsubasa) into geo-stationary transfer orbit (GTO) in February 2002. Passing through the Van Allen Belt exposed MDS-1 to severe radioactive rays in every orbit. This flight experiment measured the rate of single-event-upsets (SEUs) on a large number of stacked 64 Mbit dynamic random access memory (DRAM), and the distribution of total ionizing dose (TID) effects. As a result, we can calculate the actual SEU rate, and we confirmed the capabilities of two types of on-the-fly error detection and correction (EDAC) mechanisms. This paper presents the results of the space experiment of SSR, especially focusing on SEU analysis.

The paper addresses the problem of evaluating transient fault impact on COTS microprocessor systems. We present the problem of fault effect propagation from low logical to software and application levels. Such an analysis is needed to optimize error detection and correction mechanisms at hardware and software levels. For this purpose we use sophisticated fault injectors. The usefulness of the presented approach was proved in many experiments described in the paper. It may support hardware/software co-design.

This paper presents the design and a preliminary implementation of sfiCAN: a physical fault injector for the CAN field-bus that allows the creation of a great variety of complex fault scenarios. The fault injector replaces the CAN bus topology with a star topology, whose central element is a hub with fault injection mechanisms. The fault injector is easily configured, with great flexibility, from a PC connected to a dedicated port of the hub. For this it uses a fault-injection specification, which is translated to a configuration protocol on top of CAN. This protocol is only used in-between fault injection tests and therefore does not interfere with the execution of any test. The purpose of the fault injector is to test the behavior of the nodes of a CAN network in the presence of channel errors, in particular, of the nodes' CAN controllers and the software executing on them, for which the star topology is transparent.

One scheme for detecting faults at the processor level in a multiprocessor system (see A. Dahbura et al., 1989) works by running secondary versions of jobs on the unused, or spare, processors of the system. The authors build upon this scheme and propose three new multiprocessor allocation strategies that run a viable number of versions per job. These schemes permit online detection and, in some cases, location of faulty processors in a system, without degrading its delay/throughput performance. Two new metrics, the fault detection capability and the fault location capability, are introduced to evaluate these schemes. Extensive simulation results are provided to show that these schemes utilize spare capacity more efficiently, thereby improving upon the fault detection and location capabilities of the system. >

Large-scale distributed systems are a collection of loosely coupled computers interconnected by a communication network. They are now an integral part of everyday life with the development of large web applications, social networks, peer-to-peer systems, wireless sensor networks and many more. At such a scale, hardware components by themselves are prone to failure. Therefore, one key challenge in designing distributed storage systems is how to tolerate faults. To this end, fault tolerance mechanisms such as replication have been widely used to provide high availability for decades. More recently, many systems start supporting erasure coding for fault tolerance, which is expected to achieve high reliability at a lower storage cost compared to replication. However, the reduced storage overhead comes at the cost of more complicated recovery which hurts performance. In this paper, we study the fault tolerance mechanisms of two representative distributed file systems: HDFS and Ceph. In addition to the traditional replication, both HDFS and Ceph support erasure coding in their latest version. We evaluate the replication and erasure coding implementations in both systems using standard benchmarks and fault injection, and quantitatively measure the performance and storage overhead. Our results demonstrate the trade-offs between replication and erasure coding techniques, and serve as a foundation for building optimal storage systems with high availability as well as high performance.

The incorporation of error detection and recovery mechanisms becomes mandatory as the probability of the occurrence of transient faults increases. The detection of control flow errors has been extensively investigated in literature. However, only few works have been conducted towards recovery from control-flow errors. Generally, a program is re-executed after error detection. Although re-execution prevents faults from corrupting data, it does not allow the application to run to completion correctly in the presence of an error. Moreover, the overhead of re-execution increases prominently. The current study presents a pure-software method based on encoded signatures to recover from control-flow errors. Unlike general signature monitoring techniques, the proposed method targets not only interblock transitions, but also intrablock and inter-function transitions. After detecting the illegal transition, the program flow transfers back to the block where the error occurred, and the data errors caused by the error propagation are recovered. Fault injection and performance overhead experiments are performed to evaluate the proposed method. The experimental results show that most control flow errors can be recovered with relatively low performance overhead.

CubeSats are an established trend in the space industry. The CubeSat standard opens opportunities for rapid and low-cost access to space. The use of COTS components instead of space-hardened hardware greatly reduces the cost of CubeSat-based missions and provides the additional benefit of increasing software functionalities at a low power consumption. However, COTS components are not designed for the space environment, making CubeSats sensitive to space radiation. This means that CubeSats need additional software mechanisms to guarantee resilient behavior in the presence of space radiation. Our proposal is that such software implemented fault tolerance mechanisms must be tailored to the specific code running in each CubeSat and the logical way to achieve that is to extend the software development process for CubeSats to include the systematic resilience evaluation of software as part of the CubeSats software lifecycle process. This paper proposes a set of structured steps to enhance the classic software development process used in CubeSats, focusing particularly on the Verification and Validation (V&V) phase. The approach uses fault injection as an integral part of the development environment for CubeSats software and includes three major steps: a) sensitivity evaluation (verification) of software in the presence of faults caused by space radiation, b) strengthen of the software with targeted software implemented fault tolerance (SWIFT) mechanisms and c) validation of the effectiveness of the SWIFT mechanisms to confirm that the software is immune to space radiation faults. These added steps to the V&V process must be carried out during software development, as well as every time the CubeSat software has an update, or even a minor change, to ensure that the impact of faults caused by space radiation is tolerated by the CubeSat software. The paper demonstrates the proposed approach using three different embedded software running in the EDC (Environment Data Collection) CubeSat board, which is part (payload) of a constellation of satellites being developed by the Brazilian National Institute for Space Research (INPE). EDC use case provides a realistic insight on the effectiveness of the proposed steps. Our results show that the proposed approach can reduce the percentage of silent data corruption (the most problematic failure mode) from the range of 15% to less than 1% and even to 0% in some embedded software, meaning that the CubeSat software becomes immune to space radiation.