Improved Decoding Algorithm of Serial Belief Propagation With a Stop Updating Criterion for LDPC Codes and Applications in Patterned Media Storage

This paper presents the symbol error rate (SER) vs. signal-to-noise (SNR) ratio performance of OFDM system with QAM modulation. It has been observed that the optimal power allocation between pilot and information symbols can improve the performance gain by 2.3 dB relative to the equal power allocation between pilot and information symbols, for a system with N=3D512 sub-carriers, and a channel with L=3D40 taps. The SER performance is then compared with Rayleigh-faded as well as Rician-faded channels. It has been further concluded that the SER vs. SNR performance graph in Rayleigh-faded channel environment is better than that in Rician-faded channel. This idea implies that in OFDM case, the SER vs. SNR performance is better in scattered rich channel environments. The SER vs. SNR performance graph is degraded by equal magnitude for both equal-power and optimal-power cases, which implies that the difference between the equal-power and optimal power case is independent of the channel fading model being used. It is also observed that by varying the standard-deviation of the channel, the SER vs. SNR performance graph is not going to be affected if the channel is considered Rayleigh-faded.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

Low Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means its actual building exists that enables outer edge to be closely intended for symmetry of a channel with no memory. FPGA or Field Programmable Gate Array is based on configurable logic block (CLB) and is a semiconductor gadget that is associated by virtue of programmable interconnects. FPGAs are highly robust and can be created or designed as per the application or usefulness prerequisite of application. This research paper presents adaptable and more compatible LDPC decoder in change for other general LDPC decoder. This decoder has a completely adaptable LDPC plan in FPGA, which supports distinct codes and rate of information. The design is implemented in Xilinx ISE 14.2 software using VHDL programming and synthesized on SPARTAN 3E FPGA. Keywords: Sparse bipartite graph, threshold, Shannon limit, Very High Speed Integrated Circuit Hardware Description Language (VHDL) Cite this Article Sachit Gupta, Richa, Adesh Kumar. FPGA Implementation of LDPC Codes. Journal of Telecommunication, Switching Systems and Networks . 2018; 5(1): 21–28p.

Both polar code and Low-Density Parity-Check (LDPC) code have been adopted in 3GPP eMBB scenario. Some scholars have proposed a serial concatenation structure combining these two codes. However, the inner code needs to add redundant bits to protect the redundant bits of the outer code in the serial concatenation. In this paper, we propose a parallel concatenation code combining polar code and LDPC code on the AWGN channel, which does not distinguish the inner code from the outer code. In the proposed concatenated structure, the BP algorithm is used to decode polar code, and the output soft information of BP decoder is logarithmically processed before LDPC decoding. According to the simulation results, compared with the serial concatenated code with the same code rate and code length, the parallel concatenated code has better BER(Bit-Error-Rate) performance.

SER performance investigation of a MPPM relay-aided FSO system with three decision thresholds over EW fading channel considering pointing errors

This paper investigates the detection schemes for single-carrier underwater acoustic communications over the severe time-dispersive channels. A low-density parity-check (LDPC) code is employed for the improvement of the equalization performance. A detection scheme with Turbo conception is proposed which includes a LDPC decoder in the feedback loop of an iterative block decision feedback equalizer (IB-DFE), combining the iterative frequency domain equalization of IB-DFE with the iterative LDPC decoding. The external messages are fully exchanged between the IB-DFE and the decoder during the processing of the joint iterative equalization and decoding. The numerical results demonstrate that the decision signals with higher reliability from the LDPC decoder accelerate the convergence of the equalizer and enhance the detection performance, yielding up to 6 dB performance gains when compared with the scheme without LDPC code. Compared with the concatenated scheme in which the process of the iterative frequency domain equalization is serial concatenated with that of the iterative LDPC decoding, the combined scheme obtains about 2 dB performance gains.

In previous works, density evolution schemes have been used to design an irregular low-density parity-check (LDPC) code for the multi-input multi-output (MIMO) systems. However the code design based on the density evolution can be used only for simple code structure like LDPC codes and repeat-accumulate (RA) codes. Recently simple and accurate irregular LDPC code design method based on the extrinsic information transfer (EXIT) chart was introduced for an AWGN channel. This code design scheme is much flexible, therefore it can be used for any kind of code structure like turbo codes. In this paper we design an irregular LDPC code for a MIMO system using the EXIT chart based scheme. The EXIT charts are used to obtain the optimal edge degree distribution of the irregular LDPC code combined with the MMSE-SIC MIMO detector. This scheme can be generalized for designing the optimal iterative MIMO detector combined with any kind of channel codes including turbo codes.

In this paper, we propose a concatenated code by combining a Recursive Systematic Convolutional (RSC) code with a Low-Density Parity-Check (LDPC) code. The proposed concatenated code is encoded in parallel by an RSC encoder and an LDPC encoder without interleavers between them. When decoding the proposed concatenated code, the information bits are decoded by two decoding algorithms, and soft information is exchanged between the RSC decoder and the LDPC decoder. This allows for the elimination of wrong codewords output by each decoder. The use of an LDPC code allows us to halt the decoding process when the valid codeword is obtained. We evaluate the error rate performance of the proposed concatenated code by computer simulations. We show that the proposed concatenated code does not have a high error floor, and achieves better BLock Error Rate (BLER) performance than either conventional LDPC codes or conventional turbo codes in the high Eb/No region. We also show that since the proposed concatenated code can correct wrong codewords output by each decoder, it achieves better BLER than the regular LDPC code at the same Bit Error Rate (BER).

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

The linear programming (LP) decoding of Low-Density Parity-Check (LDPC) codes is widely concerned for its maximum likelihood (ML) features. It is that the ML decoding rule for LDPC codes can be relaxed to LP optimization problem. Therefore, this paper focus on an efficient algorithm called infeasible primal-dual interior-point (IPDIP) to solve the LP problem. In each iteration, the IPDIP algorithm obtains the predictor and corrector steps by solving the Karush-Kuhn-Tucker (KKT) equation twice. The predictor term is used to responsible for optimal solution and the corrector term keeps the current iteration away from the boundary of the feasible region. Furthermore, a modification of the centering parameter is developed to accelerate the convergence speed for the IPDIP algorithm. Simulation results of LP decoding demonstrate that the proposed IPDIP algorithm achieves beautiful bit error rate (BER) performance and good global convergence properties with less iteration number and time than other algorithms which only solve the KKT equation once by Newton method or use the not modified centering parameter.

Summary form only given. The ultimate performance limit or threshold of low-density parity-check (LDPC) codes is close to capacity over various memoryless channels (S.-Y. Chung, IEEE Trans. Info. Theory, vol. 47, pp. 657-670, 2001). Since the capacity of binary-input partial response (PR) channels is unknown, we estimate the capacity by calculating the threshold of capacity-approaching LDPC codes over these channels. We assume a BCJR equalizer for the channel and a sum-product message-passing decoder for the LDPC code. We also assume that the log-likelihood ratios (LLRs) in the channel BCJR and the LDPC decoder are Gaussian. We use our results to guide the design of decoder schedules that minimize the number of computationally expensive BCJR steps. The threshold calculation method can be used to optimize the left and right degree sequences of the LDPC code factor graph, using fast linear programming methods, to provide better thresholds than regular codes.

The joint Viterbi detector/decoder (JVDD) has been proposed as an alternative to the powerful and ubiquitous low-density parity check (LDPC) coding schemes, that are used in the majority of channel coding applications today. At shorter block lengths, the JVDD is able to outperform the state-of-the-art LDPC decoder that can be found in many of today’s systems, from deep-space communications to the digital video broadcasting standard, to the advanced television standard committee 3.0. Researchers have developed the tools to analyze the performance of the LDPC decoder, which is known as the sum-product algorithm or message passing algorithm. These tools include density evolution (DE) and extrinsic information transfer (EXIT) charts. To date, no similar such analysis exists for the JVDD. In the current paper we perform a similar preliminary analysis on the JVDD algorithm akin to what DE and EXIT charts are for the LDPC decoder. The current new analysis of the JVDD allows prediction of its probability of error based on the probability distribution functions of the metrics used within the algorithm. Our analysis plays a similar role to the abovementioned tools developed for the LDPC decoder: it allows us to predict the performance of the JVDD under various conditions (such as varying SNR’s, thresholds, and block lengths), it improves our understanding of the JVDD algorithm and the match against Monte-Carlo simulations verifies our assumptions on the main error-causing mechanisms within the JVDD.

In this paper, performance metric of orthogonal frequency division multiplexing (OFDM) system is analyzed over a composite fading channel, i.e., generalized K-fading channel. Here, OFDM system is considered which includes repetition code to enhance the wireless link performance with simplicity. Symbol error rate (SER) performance is evaluated using binary phase shift keying (BPSK) and 16-quadrature amplitude modulation (16-QAM) over generalized K-fading channel. This channel model considers Nakagami-m distribution to define multipath and gamma distribution to represent shadowing effects. Simulation results demonstrate that improved system performance can be achieved by using repetition code in severely faded environment. A comparative study of coded and uncoded system is also given in this paper. Consequently, SER performance is improved with the increase of shape parameters.

Generalized Frequency Division Multiplexing (GFDM) is a flexible multi-carrier transmission to overcome the disadvantages of OFDM. The weakness of GFDM, similarly to the other multicarrier signals, is a high PAPR, large PAPR signals can easily saturate the transmit power amplifier and cause degradation in Symbol Error Rate (SER) performance and Out-of-Band (OOB) emissions. In this paper, we analyze the effects of Non-Linear distortion using the Saleh model in GFDM. We investigate three parameters: CCDF of PAPR, frequency spectrum, and SER. The simulation results show that GFDM superior to OFDM in PAPR performance and spectrum if given the non-linear distortion. But non-linear distortion in GFDM cause SER performance is decreasing significantly while GFDM is less affected by linearity than OFDM.

In this paper, a random Low-Density Parity-Check (LDPC) code is proposed for Noncontiguous Orthogonal Frequency Division Multiplexing (NC-OFDM) Cognitive Radio (CR) systems. Unlike other encoding schemes which achieve a system code rate of only 1/4 when half of the subcarriers are active, the proposed scheme achieves a system code rate of 1/2. The LDPC code is used to enhance the data transmission rate. A new channel model comprised of a binary erasure channel concatenated with an uncorrelated fading channel and an AWGN channel is adopted for NC-OFDM CR systems. Moreover, the adopted channel model is employed with density evolution algorithm to obtain good degree distribution pairs for the LDPC code. Thereafter, a modified shortest-path algorithm is used to construct the parity-check matrix for the LDPC code. Simulation results show that the proposed LDPC code performs well in terms of both error rate and data transmission rate.