Improved Optical Profiler Metrology for Advanced Packaging

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Warpage control is a key process character for 2.5D IC without Through-Silicon Vias (TSV). For low cost package trend, TSV is not used for advanced 2.5D IC package. Yield is still an issue for 2.5D IC package, Die-Bonding (DB) last process is applied to make sure top die is bonded on good interposer. Therefore, no top die will be sacrificed for low interposer process yield, cost could be more reduced. Re-Distribution Layers (RDL) is first process for DB last interposer, then reversing wafer to do silicone removing, contact pad opening, micro pad plating, die bonding, and compound molding. Because interposer thickness is about 30~50um for 2.5D IC without TSV after silicone removing process, carrier bonding is used before silicone removing. Passivation layer is composited of organic material which coefficient of thermal expansion (CTE) is usually larger than 80ppm. Interposer warpage is substantially increased after silicone removing, which leads that carrier is a major substrate to support RDLs. Glass carrier is discussed in this study and glass CTE and passivation layer thickness are also tuned to optimize interposer warpage after silicone removing. There are two RDL layers and two PBO as passivation material in interposer. Warpage variation is a key evaluation character during this study. From our studies, glass CTE is increased from 3.2ppm to 5.7ppm, and interposer warpage value is reduced and variation could be reduced about 100um at Si removing stage, passivation thickness is increased from X to X+5um, and interposer warpage value is increased and variation could be increased about 50um at Si removing stage. Bi-layer radius formula is used to describe the warpage behavior of under bump metallization (UBM), Bonding, and Si removing stages and is well matched NTI package warpage behavior at UBM and Si removing stages. For Bonding warpage behavior, bi-layer radius theory is interfered by non-perfect adhesion at glue layer, but warpage variation trend is still matched with warpage experiment.

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible. However, by virtue of the new process steps and technologies required to get to 3-D packaged materials, such as through silicon vias (TSVs), wafer thinning and handling processes and requirements for alternative dielectric materials, many opportunities have arisen. Expectations are that many devices that follow a flip chip ball grid array (FCBGA) flow or WLCSP will adopt an embedded technology strategy for future generations. FOWLP has several advantages, over FCBGA and WLCSP including potential for system in package (SIP) configurations and 3-D integration, the ability to overcome pad limitation issues, and shorter interconnections and so higher electrical performance. However, to gain these advantages, requirements for processing will change due to the significant demands imposed on the materials used as permanent dielectric layers and the photoresists used in the fabrication processes. Cleaning chemistry must be designed to remove challenging films such as photoresists and residues created during other process steps; yet preserve the exposed metals such as the bond pads and Cu redistribution lines, as well as the permanent dielectrics. Device reliability and performance is heavily dependent on the proper working of all these components. The focus of this paper is to identify a manufacturable and reliable process and process window for removal of positive photoresists and residues in formation of under bump metallization (UBM) and contact pads in wafer level packaging (WLP). Our objective is to discuss a proven process that has been successfully implemented into a manufacturing environment. It has improved robustness and reliability over past-used solutions due to decreased sensitivity to moisture contamination, a significant cause of defects in many device applications.

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm2 is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

Advanced through silicon vias for hybrid pixel detector modules

Increasing demand for new and more advanced electronic products, with smaller form factor and superior functionality and performance, while reducing the cost, has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging, using z-axis through silicon via (TSV) stacking concept has been and continues to be investigated by many of the semiconductor manufacturers and research institutes and is believed to be one of the most promising, if not the most promising concept that could successfully address the limitations of today's packaging technologies. There is a continuous increase of interest in development and study of applicability of this new chip stacking approach to existing and future devices; currently, more than fifty companies worldwide are involved in some sort of 3D TSV packaging developments. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes, applications that have to be well understood and integrated in order to successfully be applied. This paper will address various electrodeposition processes applied to form 3D interconnects, from TSV deposition, which is the main metallization step that stays at the hearth of this new technology, to other metallization steps for additional connections, such as bumping and redistribution layers, already well known and applied processes in current wafer level packaging (WLP) applications. Advantages and difficulties associated with each of these technologies, with more focus on 3D vertical integration using TSV copper interconnect, including the approaches taken to overcome them, will be presented. Deposition conditions for bumping were optimized in order to enable higher deposition rates. For other through- mask applications, such as redistribution lines (RDL), the complexity of the pattern, deposition rate, chemical formulation and process parameters were found to have a significant effect on within-die (WID) thickness distribution. In case of WLP structures of thick metal and high aspect ratios, seed layer uniformity proved to be essential for achieving void-free deposition. Void-free structures, especially for high aspect ratio vias seeded with dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), seem difficult to obtain. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB) can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition process along the entire sidewall of the via, at significantly lower costs. This paper will present TSV structures obtained with wet chemical processes applications for both seed layer and via filling. Besides seed layer uniformity, additional factors were identified to also be critical for successfully filling deep vias. They are: via profile, wettability of vias, superior performance of chemistries and high performance equipment. By selecting the most appropriate deposition methods and optimizing the chemical formulations together with the process parameters, void-free TSV structures can be obtained.

Internet of things (IoT) will influence all areas from consumer to health care to building and home automation and to observation. IoT enables direct communication between objects via internet. The main functional blocks of IoT devices are sensing, data transmitting, processing and analysis and subsequent actuation. As a result such a system will consist of sensors, actuators, wireless connection, data processing, power management, energy harvesting, memory and software. A total market volume of almost 400 Bio US$ is predicted for 2024 whereof about 12Bio US$ are expected for IoT sensors (Yole2014)). The main challenges are to reduce footprint (e.g. wearables, swarm), reduce costs of system, improve reliability and provide better performance. For example the costs of today's smart sensor systems are in the 100–1000US$ range and for 2024 an ASP in the 1US$ $ level is expected (Yole2014). To enable this, a high level of integration is needed for the next generations of IoT sensors. This will on one hand reduce costs and form factor but also enable multi sensors devices. More than Moore integration of functions offers the potential to meet both performance and cost targets for mass-market adoption. In addition to SoC (System on Chip) and SiP (System in Package) heterogeneous 3D integrations will be key enablers. 3D integration with the main technology bricks like TSV (Through Silicon Via), RDL (Redistribution Layer), D2W (Die to Wafer) and W2W (Wafer to Wafer) stacking and embedding allows to combine different technologies - different CMOS notes, MEMS, photonics, etc. At the same time expensive single die packaging can be avoided. The presentation will focus on reviewing 3D integration technologies and their potential for IoT from the perspective of a sensor solution provider.

The elimination of lead from solders for flip‐chip attachment has necessitated many new studies on the reliability of the resultant systems. There are many lead‐free solder material systems. However, most of them contain a large proportion of tin. The tin in the solder reacts with the copper layer present in some types of under bump metallisation (UBM) depleting the UBM of copper, and thereby causing loss of adhesion and a weak interface. In this work, the relative reliability of Cr/Cu/Cu and Cr/Cu/Cu/Ni UBM systems was studied. The UBM systems were deposited with an electroplated Sn‐3.5Ag lead‐free solder alloy. The results conclusively showed that the Cr/Cu/Cu/Ni UBM system is a better choice for the Sn‐3.5Ag lead‐free solder. In the Cr/Cu/Cu/Ni UBM system, the thickness of the nickel layer was found to be an important parameter. Multiple reflow and high temperature storage test results showed that serious depletion of the UBM layer could occur if the UBM layers were not optimised. The thermo‐mechanical reliability of Ni‐based UBM bumps showed promising results up to 1,500 temperature cycling.

With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore's Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps' reliability, through-silicon vias' (TSVs) and redistribution layers' (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing.

In this paper a low temperature ‘via-last’ technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front side to back side alignment will be described. In a second part the steps of the Through Silicon Vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. A special focus will be done on this paper on the TSV metallization step and especially on the chemical seed layer etching. A study has been achieved in this project in order to optimize this part of the process and the results will be shown. Then, morphological and electrical characterizations of the via-last technology will be presented and discussed. Finally, a picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be shown.

Two vertical transitions with through silicon vias (TSVs) in 3D die stack are designed and their high frequency electrical characteristics are presented in this paper. The two vertical transitions consist of TSVs for obtaining electrical connection between the die front side and back side. Back side redistribution layer is eliminated in the designs to simplify the fabrication process without sacrificing the electrical performance. Design considerations and guidelines are provided to design high speed TSV structure up to 50 GHz. Different kinds of transmission line interconnects (for instance, microstrip line and coplanar waveguide) are implemented at the input/output extensions for different applications. For both vertical transition designs, the simulated insertion loss is better than 0.65 dB up to 50 GHz while good impedance matching from DC to 50 GHz is obtained with the simulated return loss greater than 14 dB.

In this paper, a full channel simulation model of interposer and organic substrate is established. The TSV (through silicon via) interposer provides high-bandwidth, low-latency interconnection to accomplish higher performance and reach smaller size of the semiconductor devices. For 2.5D packaging, it's extremely necessary and pressing to estimate the electrical property and optimize the structure for TSV interposer. The model of ground-signal-signal-ground (GSSG) coplanar lines of differential pair in redistribution layer (RDL) on the interposer with TSVs is simulated by Ansoft's HFSS. In addition, another strip line model of this differential pair in organic substrate is simulated. Then a co-simulation method of the full channel is proposed utilizing Agilent's ADS. By using the simulation approach, the signal quality of this channel is presented and some signal integrity (SI) issues are discussed by analyzing the S-parameter and eye diagram.

The electroplating solder bumping process offers fine pitch, high reliability, and cost effective advantages for flip-chip technology. In this technology, under bump metallization (UBM) is required for chemical solder deposition and mechanically reliable solder contact to Al pads. An evaporated Cr/phased CrCu/Cu structure UBM has been used with 95Pb/5Sn and also with 37Pb/63Sn solder for flip-chip interconnection. In this study, the intermediate CrCu layer is modified using various sputtering techniques, and the underlying Cr adhesion layer is compared with TiW. Six UBM systems were selected, and their interfacial reaction and bump shear strength were investigated using 100 /spl mu/m and 50 /spl mu/m size electroplated Pb/63Sn solder bumps. The results demonstrate that the final Cu layer should have a minimum thickness, more than 0.8 /spl mu/m, for interface stability on CrCu based UBMs. Intermetallic compound growth and CrCu layer interface changes are more severe after 20 min reflow at 210/spl deg/C compared with 1000 h aging at 125/spl deg/C. Especially for small size bumps, a more stable interface between UBM and solder bump is required.