Improving GPU Energy Efficiency through an Application-transparent Frequency Scaling Policy with Performance Assurance

Non-volatile memories, such as Phase Change Memories (PCM), have interesting energy properties. In effect, their static energy consumption is negligible while the consumed dynamic energy depends on the performed operation (read/write). Several Dynamic Voltage and Frequency Scaling (DVFS) mechanisms have been proposed to optimize the energy consumption of memory-bound tasks in embedded systems. In a hybrid memory, using both DRAM and PCM, these DVFS strategies need to be adapted to take into account the different energy behaviors of both memories. In this paper, we propose a Hybrid Memory-Aware DVFS strategy (HyMAD) to reduce the energy consumption for memory bound tasks. This mechanism relies on both the rate of PCM write operations and the overall memory access rate to tune the CPU frequency. HyMAD takes also into account the priority of a task to tune the "performance loss" / "energy efficiency" trade-off. We compared HyMAD with a state-of-the-art technique by evaluating the Energy-Squared-Delay product ( ED2P ). HyMAD ED2P enhancement was evaluated between 2--45% as compared to a system without DVFS and up to 20% as compared to a state-of-the-art DVFS strategy.

Dynamic voltage and frequency scaling (DVFS) is a means to adjust the computing capacity and power consumption of computing systems to the application demands. DVFS is generally useful to provide a compromise between computing demands and power consumption, especially in the areas of resource-constrained computing systems. Many modern processors support some form of DVFS. In this article, we focus on the development of an execution framework that provides lightweight DVFS support for reactive stream processing systems (RSPS). RSPs are a common form of embedded control systems, operating in direct response to inputs from their environment. At the execution framework, we focus on support for many-core scheduling for parallel execution of concurrent programs. We provide a DVFS strategy for RSPs that is simple and lightweight, to be used for dynamic adaptation of the power consumption at runtime. The simplicity of the DVFS strategy became possible by the sole focus on the application domain of RSPs. The presented DVFS strategy does not require specific assumptions about the message arrival rate or the underlying scheduling method. While DVFS is a very active field, in contrast to most existing research, our approach works also for platforms like many-core processors, where the power settings typically cannot be controlled individually for each computational unit. We also support dynamic scheduling with variable workload. While many research results are provided with simulators, in our approach, we present a parallel execution framework with experiments conducted on real hardware, using the single-chip cloud computer many-core processor. The results of our experimental evaluation confirm that our simple DVFS strategy provides potential for significant energy saving on RSPs.

Modern data centers must provide performance assurance for complex system software such as multi-tier web applications. In addition, the power consumption of data centers needs to be minimized to reduce operating costs and avoid system overheating. Various power-efficient performance management strategies have been proposed based on dynamic voltage and frequency scaling (DVFS). Virtualization technologies have also made it possible to consolidate multiple virtual machines (VMs) onto a smaller number of active physical servers for even greater power savings, but at the cost of a higher overhead. This paper proposes a performance-controlled power optimization solution for virtualized data centers with multi-tier applications. While existing work relies on either DVFS or server consolidation in a separate manner, our solution utilizes both strategies for maximized power savings by integrating feedback control with optimization strategies. At the application level, a multi-input-multi-output controller is designed to achieve the desired performance for applications spanning multiple VMs, on a short time scale, by reallocating the CPU resources and DVFS. At the data center level, a power optimizer is proposed to incrementally consolidate VMs onto the most power-efficient servers on a longer time scale. Empirical results on a hardware testbed demonstrate that our solution can effectively achieve performance-assured power savings. Extensive simulation results, based on a trace file of 5,415 real servers, demonstrate the efficacy of our solution in large-scale data centers.

Graphics processor (GPU) architectures have evolved rapidly in recent years with increasing performance demanded by 3D graphics applications such as games. However, challenges exist in integrating complex GPUs into mobile devices because of power and energy constraints, motivating the need for energy efficiency in GPUs. While a significant amount of power optimisation research effort has concentrated on the CPU system, GPU power efficiency is a relatively new and important area because the power consumed by GPUs is similar in magnitude to CPU power. Power and energy efficiency can be introduced into GPUs at many different levels: 1) Hardware component level - queue structures, caches, filter arithmetic units, interconnection networks, processor cores, etc., can be optimised for power. 2) Algorithm level - the deep and complex graphics processing computation pipeline can be modified to be energy aware. Shader programs written by the user can be transformed to be energy aware. 3) System level - co-ordination at the level of task allocation, voltage and frequency scaling, etc., requires knowledge and control of several different GPU system components We outline two strategies for applying energy optimisations at different levels of granularity in a GPU: (1) Texture Filter Memory (TFM) - an energy-efficient addition to the texture memory hierarchy component; and (2) an overall system level Dynamic Voltage and Frequency Scaling (DVFS) based energy reduction strategy based on an accurate tile-level slack prediction. Texture Filter Memory is an augmentation of the standard GPU texture cache hierarchy. Instead of a regular data cache hierarchy, we employ a small first level register based structure that is optimised for the relatively predictable memory access stream in the texture filtering computation. Predictability of the memory access patterns leads us to reduce power by using a simpler register access structure. Power is saved by avoiding the expensive tag lookup and comparisons present in regular caches. Further, the texture filter memory is a very small structure, whose access energy is much smaller than a data cache of similar performance. Dynamic Voltage and Frequency Scaling, an established energy management technique, can be applied in GPUs by first predicting the workload in a given frame, and, where sufficient slack exists, lowering the voltage and frequency levels so as to save energy while still completing the work within the frame rendering deadline. We apply DVFS in a tiled graphics renderer, where the workload prediction and voltage/frequency adjustment is performed at a tile-level of granularity, which creates opportunities for on-the-fly correction of prediction inaccuracies, ensuring high frame rates while still delivering low power. Tile-level energy management schemes are distinctly superior to schemes that work at the granularity of the entire frame in terms of energy saving and quality of the rendering measured in terms of frames rendered per second. The prediction mechanism relies both on the history - workload observed for the tile in recent frames, as well as rank - a quantification of the tile workload based on the frame structure, consisting of geometry, pixel shading, texture, and raster operations workloads.

Dynamic Voltage and Frequency Scaling (DVFS) is a method to save energy consumption of electronic devices and to protect them against overheating by automatic sensing and adaptation of their energy consumption. This can be accomplished either on the program instruction level for electronic devices or on the task or job level for server clusters. This paper models DVFS on the job level and through which Service Levels Objectives can be guaranteed with respect to prescribed mean or quantiles of service delays according to given Service Level Agreements (SLA) between user and service provider. The two parameters V (voltage) and f (frequency) cannot be changed independently of each other; typically only several combinations of V and f values are implemented in hardware for several power states. In this paper a novel analysis of operating DVFS is suggested for Server Clusters of Cloud Data Centers (CDC) under prescribed bounds of service level objectives which are defined by SLAs. The method is based on the theory of queuing models of the type GI/G/n for a server cluster to establish a relationship between SLA parameters and the power consumption and is performed for the example of the Intel Pentium M Processor with Enhanced SpeedStep Power Management. As result of this method precise bounds are provided for the load ranges of service request rates $\lambda$ for each power mode which guarantee minimum power consumption dependent on given SLA values and job arrival and service statistics. As the instantaneous load in a CDC can be highly volatile the current load level is usually monitored by periodic sensing which may result in a rather high frequency of DVFS range changes and corresponding overhead. For that reason an automated smoothing method is suggested which reduces the frequency of DVFS range changes significantly. This method is based on a Finite State Machine (FSM) with hysteresis levels.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

Power consumption has become a major design constraint in the embedded systems domain and techniques such as dynamic voltage and frequency scaling (DVFS) have emerged to enhance the system's power and energy efficiency. DVFS-enabling voltage regulators influence the performance, power and energy efficiency of such systems, however, this impact is often neglected or considered late in the design process. In this work, we propose DVFS hardware extensions to a power emulation approach for modeling the voltage regulator behavior, which allows for performance, power and energy efficiency investigations of DVFS-enabled embedded systems. The power emulation approach delivers real-time power information in an early design phase, which allows for the exploration of DVFS efficiency before silicon is available. This offers greater freedom to designers to determine the most apt voltage regulator yielding a system that meets performance, power and energy constraints.

Dynamic Voltage and Frequency Scaling (DVFS) approach is proposed to control the power consumption in devices of different types like from a small mobile device to a huge server. This paper aims to study the effect of parallel execution of two benchmark applications, one the Stanford Single Source benchmarks (lightweight parallel code) and, Stanford Parallel Applications for Shared Memory (SPLASH-2) programs (heavy real-time data streaming parallel applications that run on multi -core clusters) on DVFS for dark silicon ameliorating. Both these benchmarks executed on a gem5 Full System simulator, booting a linaro based linux kernel. To get a holistic big picture of the power and thermal properties of systems that run on DVFS, in addition to the control feature present in gem 5, a power-estimation framework used for the evaluation of the efficiency of various DVFS policies, the MCPAT and Hotspot is also employed. Based on the execution of Stanford workloads DVFS model is analyzed in terms of memory footprint and on other critical processor performance metrics, like running time per core, bus latency, number of read, writes, access time, cache hit or miss. The gem5 is extended with full DVFS support by the addition of a framework in which easy power-model integration can be done.

The widespread use of Wireless Sensor Networks (WSN) in Internet of Things (IoT) causes energy efficiency issues. This paper proposes an AI-based solution to this problem. The propose an AI-Driven Power Optimization framework for IoT-enabled WSN using Deep Q-Network (DQN) and Dynamic Voltage and Frequency Scaling (DVFS). These techniques can adapt to changing network conditions and reduce power consumption when used together. Sensor nodes provide environmental parameters, battery status, and network behavior data to the AI-driven framework DQN is implemented after data preprocessing to learn and make power management decisions using reinforcement learning. Neural network-driven agent operates in a state and action space. It optimizes energy use with rewards. Real-time hardware power adjustment is done using DVFS. DVFS precise control and AI-driven decision-making create a comprehensive power optimization strategy. AI adapts to new challenges and optimizes network lifespan by improving its power management policies. Experimental implementations of the proposed framework show significant energy savings, network lifespan extension, and QoS improvements. AI-Driven Power Optimization in IoT-enabled WSN is proven effective and flexible. This study shows the potential of AI, specifically DQN and DVFS, in IoT-enabled WSN. This AI-Driven Power Optimization framework addresses energy efficiency and improves IoT sensor networks. AI improves power optimization in IoT-enabled WSN making IoT deployments more sustainable and resilient.

Energy efficiency and energy proportional computing have become major constraints in the design of modern exascale platforms. Dynamic voltage and frequency scaling (DVFS) is one of the most commonly used and effective techniques to dynamically reduce power consumption based on workload characteristics. Many energy-saving strategies, however, employ DVFS without considering its applicability level in a given multicore processor. The present work demonstrates that disregarding the DVFS granularity as a design constraint while developing energy-saving strategies may reduce the efficacy of the strategy for certain application classes. Specifically, DVFS applicability levels (called granularities) are determined here for three different Intel processor microarchitectures. Then, the degradation in energy savings is evaluated if the DVFS granularity is disregarded. Experiments were conducted on the widely used quantum chemistry packages, General Atomic and Molecular Electronic Structure System (GAMESS) and NWChem, and show that, for granularity unaware energy-saving techniques, the overall energy consumption may increase by as much as 19%.

Performance-controlled server consolidation for virtualized data centers with multi-tier applications

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

Dynamic Voltage and Frequency Scaling (DVFS) is widely used in today's mobile devices. Commonly adopted OS level DVFS policies usually operate with high sampling and adjustment frequency in order to compensate for the lack of information from applications. In this paper, we consider the application of video decoding and propose a method that enables DVFS at a coarse time granularity by taking advantage of application level semantics. Using machine learning, we build a prediction model for the choice of CPU frequency based on the estimated workload and the progress of execution. We show that with our method, the system is able to perform DVFS with a frequency of only around 1 Hz, abiding by the practical constraints imposed by existing operating systems, but still saves an average of 40.1% in energy consumption compared with the execution at nominal speed. Further, we argue that the law of diminishing returns applies if we increase the frequency at which DVFS operates, and thus it may be costly and impractical to perform application level DVFS at a very fine time granularity.

The surge in demand for energy-efficient computing has spurred the exploration of cutting-edge techniques to optimize power consumption in modern computing systems. Though the traditional implementation of Dynamic Voltage and Frequency Scaling (DVFS) has proven effective, their traditional implementations lack adaptability, limiting their ability to fully exploit dynamic workload variations. This research presents an innovative solution by integrating proposed Reinforcement Learning (RL) algorithms into DVFS, addressing the limitations of conventional methods. The proposed RL algorithm employs Q-Iearning, a model-free RL technique, to iteratively learn the optimal policy for adjusting CPU voltage and frequency. Our customized algorithm enables autonomous real-time adjustments of voltage and frequency levels, showcasing a remarkable 20% power saving compared to conventional DVFS. The model's adaptability is evident in its capacity to achieve optimal configurations across diverse workloads, emphasizing RL's potential for enhancing energy efficiency in computing systems. As energy efficiency gains paramount importance, this research underscores the pivotal role of RL, in achieving sustainable and optimal performance in computing systems.

The development of Cloud computing applications has initiated a substantial influence on the data center expansion around the world. This expansion has led to an increase in energy consumption within the different data centers. Aware of the environmental and financial impact of the energy efficiency, several research studies have tackled the problem of the energy efficiency at the level of the hardware as well as scheduling algorithms. However, the majority of the proposed solutions such as Dynamic Voltage and Frequency Scaling (DVFS) have demonstrated a negative effect on response time where most Cloud applications required a high responsiveness. This paper suggests an energy efficiency solution for Cloud computing by applying a fast and smart algorithm. Firstly, the paper provides an evaluation of the energy efficiency within the Cloud environment through the Taguchi experience plan. Secondly, the article introduces a bee colony scheduling algorithm which aims to optimize the energy efficiency while guaranteeing an optimum response time. The validation results acquired from the GreenCloud simulator emphasize the effectiveness of the suggested scheduling analysis methodology.