In the recent past, there has been a steady growth of the market for consumer embedded devices such as cell phones, GPS and portable multimedia systems. In embedded systems, digital, analog and software components are combined on a single chip, resulting in increasingly complex designs that introduce richer functionality on smaller devices. As a consequence, the potential insertion of errors into a design becomes higher, yielding an increasing need for automated analog and mixed-signal validation tools. In the purely digital setting, formal verification based on properties expressed in industrial specification languages such as PSL and SVA is nowadays successfully integrated in the design flow. On the other hand, the validation of analog and mixed-signal systems still largely depends on simulation-based, ad-hoc methods. In this tutorial, we consider some ingredients of the standard verification methodology that can be successfully exported from digital to analog and mixed-signal setting, in particular property-based monitoring techniques. Property-based monitoring is a lighter approach to the formal verification, where the system is seen as a “black-box” that generates sets of traces, whose correctness is checked against a property, that is its high-level specification. Although incomplete, monitoring is effectively used to catch faults in systems, without guaranteeing their full correctness.In the first part of the tutorial, we present a technique for property-based analog and mixed-signal monitoring. In the heart of the framework lies signal temporal logic STL, that is a high-level specification language allowing to express transient properties of analog, mixed and timed signals. STL is an extension of the real-time metric interval temporal logic MITL, where one can specify temporal relations between relevant “events” in the continuous signals that are captured using numerical predicates. We then present procedures for automatic translation of arbitrary STL specifications into monitors, i.e. programs that check the correctness of a set of simulation traces with respect to the given property. We introduce analog monitoring tool AMT that implements the presented monitoring techniques and illustrate the usefulness and the limitations of the approach on two industrial case studies, considering properties of a FLASH memory cell and a DDR2 memory interface.Although the STL framework implemented in AMT provides a theoretical basis for analog and mixed-signal verification, it is not adequate for industrial-strength verification. The DDR2 example shows that STL lacks the expressiveness to specify complex timing relationships required by industrial designs. The STL framework provides real-time extensions to linear temporal logic, but it does not provide extensions to the regular expressions present in both PSL and SVA. However, the industrial interest in the methodology resulted in the creation of the A-SVA sub-committee of the Accellera Verilog-AMS committee that is investigating extending SVA with features that would enable industrial-strength property-based monitoring of analog and mixed-signal systems. This includes in particular real-time regular expressions, local variables, and requirements for the properties to access accurate continuous values. The committee have agreed upon a preliminary syntax and semantics for real-time regular expressions and local variables. They are in the process of integrating the real-time regular expressions with the digital and real-time properties. These results are expected to be integrated into the next revisions of Verilog-AMS and SystemVerilog.
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