Improving the throughput of the AES algorithm with multicore processors

Parallel programming on multi-core processors has become the industry's biggest software challenge. This paper proposes a novel parallel architecture for executing sequential programs using multi-core pipelining based on program slicing by a new memory/cache dynamic management technology. The new architecture is very suitable for processing large geospatial data in parallel without parallel programming. This paper presents a new architecture for parallel computation that addresses the problem of needing to relocate data from one memory hierarchy to another in a multi-core environment. A new memory management technology inserts a layer of abstraction between the processor and the memory hierarchy, allowing the data to stay in one place while the processor effectively migrates as tasks change. The new architecture can make full use of the pipeline and automatically partition data then schedule them onto multi-cores through the pipeline. The most important advantage of this architecture is that most existing sequential programs can be directly used with nearly no change, unlike conventional parallel programming which has to take into account scheduling, load balancing, and data distribution. The new parallel architecture can also be successfully applied to other multi-core/many-core architectures or heterogeneous systems. In this paper, the design of the new multi-core architecture is described in detail. The time complexity and performance analysis are discussed in depth. The experimental results and performance comparison with existing multi-core architectures demonstrate the effectiveness, flexibility, and diversity of the new architecture, in particular, for large geospatial data parallel processing with the examples of Digital Elevation Model (DEM) generation from Light Detection And Ranging (LIDAR) dataset.

As multicore processors become the default, researchers are aggressively looking for program execution models that make it easier to use the available resources. Multithreaded programming models that rely on statically-parallel programs have gained prevalence. Most of the existing research is directed at adapting and enhancing such models, alleviating their drawbacks, and simplifying their usage. This paper takes a different approach and proposes a novel execution model to achieve parallel execution of statically-sequential programs. It dynamically parallelizes the execution of suitably-written sequential programs, in a dataflow fashion, on multiple processing cores. Significantly, the execution is race-free and determinate. Thus the model eases program development and yet exploits available parallelism. This paper describes the implementation of a software runtime library that implements the proposed execution model on existing commercial multicore machines. We present results from experiments running benchmark programs, using both the proposed technique as well as traditional parallel programming, on three different systems. We find that in addition to easing the development of the benchmarks, the approach is resource-efficient and achieves performance similar to the traditional approach, using stock compilers, operating systems and hardware, despite the overheads of an all-software implementation of the model.

Optimization in multicore processor environment is significant in real world dynamic applications, as it is crucial to find and track the change effectively over time, which requires an optimization algorithm. In massively parallel processing multicore processor architectures, like other population based metaheuristics Constraint based Bacterial Foraging Particle Swarm Optimization (CBFPSO) scheduling can be effectively implemented. In this study we discuss possible approaches to parallelize CBFPSO in multicore system, which uses different constraints; to exploit parallelism are explored and evaluated. Due to the ability of keeping good balance between convergence and maintenance, for real world applications, among the various algorithms for parallel architecture optimization CBFPSOs are attracting more and more attentions in recent years. To tackle the challenges of parallel architecture optimization, several strategies have been proposed, to enhance the performance of Particle Swarm Optimization (PSO) and have obtained success on various multicore parallel architecture optimization problems. But there still exist some issues in multicore architectures which require to be analyzed carefully. In this study, a new Constraint based Bacterial Foraging Particle Swarm Optimization (CBFPSO) scheduling for multicore architecture is proposed, which updates the velocity and position by two bacterial behaviours, i.e., reproduction and elimination dispersal. The performance of CBFPSO is compared with the simulation results of GA and the result shows that the proposed algorithm has pretty good performance on almost all types of cores compared to GA with respect to completion time and energy consumption.

Scaling up algorithms or applications in data mining studies for massive datasets to improve the computing performance is becoming crucial since we've stepped into Big Data era. For community detection, which is one of the most important topics in data mining, numerous algorithms were proposed for a better exploration of the complex networks in real world and researchers keep working on improving their computing performance by parallel programming. Speaker-listener Label Propagation Algorithm (SLPA) is a sequential linear time algorithm for overlapping community detection. In this work, we proposed a new approach to parallelize and optimize SLPA. We make it more efficient through reducing the computational complexity of one of its computing kernels and providing with a better way to get memory access during parallel execution. Evaluation of abundant experiments demonstrates our implementation's better scalability on multi-core CPUs than prior work.

With an increasing number of shared memory multicore processor architectures, there is a requirement for supporting multiple architectures in automatic parallelizing compilers. The OSCAR (Optimally Scheduled Advanced Multiprocessor) automatic parallelizing compiler is able to parallelize many different sequential programs, such as scientific applications, embedded real-time applications, multimedia applications, and more. OSCAR compiler’s features include coarse-grain task parallelization with earliest execution condition analysis, analyzing both data and control dependencies, data locality optimizations over different loop nests with data dependencies, and the ability to generate parallelized code using the OSCAR API 2.1. The OSCAR API 2.1 is compatible with OpenMP for SMP multicores, with additional directives for power control and supporting heterogeneous multicores. This allows for a C or Fortran compiler with OpenMP support to generate parallel machine code for the target multicore. Additionally, using the OSCAR API analyzer allows a sequential-only compiler without OpenMP support to generate machine code for each core separately, which is then linked to one parallel application. Overall, only little configuration changes to the OSCAR compiler are needed to run and optimize OSCAR compiler-generated code on a specific platform. This paper evaluates the performance of OSCAR compiler-generated code on different modern SMP multicore processors, including Intel and AMD x86 processors, an Arm processor, and a RISC-V processor using scientific and multimedia benchmarks in C and Fortran. The results show promising speedups on all platforms, such as a speedup of 7.16 for the swim program of the SPEC2000 benchmarks on an 8-core Intel x86 processor, a speedup of 9.50 for the CG program of the NAS parallel benchmarks on 8 cores of an AMD x86 Processor, a speedup of 3.70 for the BT program of the NAS parallel benchmarks on a 4-core RISC-V processor, and a speedup of 2.64 for the equake program of the SPEC2000 benchmarks on 4 cores of an Arm processor.Keywordsmulticoreparallelizing compilerOSCARmultiple platformsshared memory

In scientific computing, solving systems of linear equations is a very essential and widely used complex problem. Finding an optimal solution, using various algorithms, to these highly computation problems is very important. As the number of variables increases, the complexity of these problems also increases. These huge amounts of computations require High Performance Computing (HPC) systems, where efficient task distribution and accurate performance analysis are highly required on using these systems. In this paper, the computation performance using multicore architecture and Graphics Processing Units (GPUs) are compared with an analysis and expectations for the future of the new multicore systems. The number of cores in GPUs is extremely larger compared to the multicore architecture, while the memory overhead degrades the performance of GPUs dramatically. The expected scalability of the multicore system architecture tends to have better performance than GPUs.

The upcoming generation of computer hardware poses several new challenges for database developers and engineers. Software in general and database management systems (DBMSs) in particular will no longer benefit from performance gains of future hardware due to increase clock speed, as it was the case for the last 35 years; instead, the number of cores per CPU will increase steadily. Today’s approach is to run each query on a single core or only a few different cores using parallel query execution. This approach suffers from several problems (e.g. contention problem) and therefore leads to poor speed up and scale up behavior. These observations open several important research questions on how to use the new multi-core CPU architecture for improving the overall performance of DBMSs. This paper outlines our approach for query processing on multi-core CPU architectures. We present an abstract architecture view for multi-core CPUs, meta operators to control and to interact with the hardware, and a new query operator model that makes use of the meta operators to control the parallel execution of a query over different cores. We illustrate how each of these parts fits in our framework for query processing on multi-core architectures.

While multicore architectures are used in the whole product range from server systems to handheld computers, the deployed software still undergoes the slow transition from sequential to parallel. This transition, however, is gaining more and more momentum due to the increased availability of more sophisticated parallel programming environments. Combined with the ever increasing complexity of multicore architectures, this results in a scheduling problem that is different from what it has been, because concurrently executing parallel programs and features such as non-uniform memory access, shared caches, or simultaneous multithreading have to be considered. In this paper, we compare different ways of scheduling multiple parallel applications on multicore architectures. Due to emerg- ing parallel programming environments, we primarily consider applications where the parallelism degree can be changed on the fly. We propose TACO, a topology-aware scheduling scheme that combines equipartitioning and coscheduling, which does not suffer from the drawbacks of the individual concepts. Additionally, TACO is conceptually compatible with contention-aware scheduling strategies. We find that topology-awareness increases performance for all evaluated workloads. The combination with coscheduling is more sensitive towards the executed workloads and NUMA effects. However, the gained versatility allows new use cases to be explored, which were not possible before.

While multicore architectures are used in the whole product range from server systems to handheld computers, the deployed software still undergoes the slow transition from sequential to parallel. This transition, however, is gaining more and more momentum due to the increased availability of more sophisticated parallel programming environments. Combined with the ever increasing complexity of multicore architectures, this results in a scheduling problem that is different from what it has been, because concurrently executing parallel programs and features such as non-uniform memory access, shared caches, or simultaneous multithreading have to be considered. In this paper, we compare different ways of scheduling multiple parallel applications on multicore architectures. Due to emerging parallel programming environments, we primarily consider applications where the parallelism degree can be changed on the fly. We propose TACO, a topology-aware scheduling scheme that combines equipartitioning and coscheduling, which does not suffer from the drawbacks of the individual concepts. Additionally, TACO is conceptually compatible with contention-aware scheduling strategies. We find that topology-awareness increases performance for all evaluated workloads. The combination with coscheduling is more sensitive towards the executed workloads and NUMA effects. However, the gained versatility allows new use cases to be explored, which were not possible before.

The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to parallelize, remains important. Proposed asymmetric multicore processors statically dedicate hardware to improve sequential performance, but at the cost of reduced parallel performance. However, several proposed mechanisms provide the best-of-both-worlds by combining multiple cores into a single, more powerful processor for sequential code. For example, Core Fusion merges multiple cores to pool caches and functional units, and Intel's Turbo Boost raises the clock speed of a core if the other cores on a chip are powered down.These reconfiguration mechanisms have two important properties. First the set of available cores and their capabilities can vary over short time scales. Current operating systems are not designed for rapidly changing hardware: the existing hotplug mechanisms for reconfiguring processors require global operations and hundreds of milliseconds to complete. Second, configurations may be mutually exclusive: using power to speed one core means it cannot be used to speed another. Current schedulers cannot manage this requirement.We present Chameleon, an extension to Linux to support dynamic processors that can reconfigure their cores at runtime. Chameleon provides processor proxies to enable rapid reconfiguration, execution objects to abstract the processing capabilities of physical CPUs, and a cluster scheduler to balance the needs of sequential and parallel programs. In experiments that emulate a dynamic processor, we find that Chameleon can reconfigure processors 100,000 times faster than Linux and allows applications full access to hardware capabilities: sequential code runs at full speed on a powerful execution context, while parallel code runs on as many cores as possible.

Nowadays, many security algorithms are used for security purpose. Encryption provides a solution in security system. In recent years, security of network had important issue. My research work shows the performance of the encryption methods like AES, DES, and RSA algorithms. By experiment result, it is concluded that RSA takes longest time for encryption and AES algorithm take shortest encryption time. We also conclude that decryption of AES also is excellent in comparison with other algorithms. There is no single method that will provide all the services specified. In this research, we identify that an important mechanism which will help different types of integrity is called cryptographic technique.

The growing number of processing cores in a single CPU is demanding more parallelism from sequential programs. But in the past decades few work has succeeded in automatically exploiting enough parallelism, which casts a shadow over the many-core architecture and the automatic parallelization research. However, actually few work was tried to understand the nature, or amount, of the potentially available parallelism in programs. In this paper we will analyze at runtime the dynamic data dependencies among superblocks of sequential programs. We designed a meta re-arrange buffer to measure and exploit the available parallelism, with which the superblocks are dynamically analyzed, reordered and dispatched to run in parallel on an ideal many-core processor, while the data dependencies and program correctness are still maintained. In our experiments, we observed that with the superblock reordering, the potential speedup ranged from 1.08 to 89.60. The results showed that the potential parallelism of normal programs was still far from fully exploited by existing technologies. This observation makes the automatic parallelization a promising research direction for many-core architectures.

Due to advancement of Information and Technology, Artificial Intelligence and Internet of things, Space Technology and E-Commerce world that changes the life of human being as because of that it is possible to interact with people by electronic means to everybody, every time, everywhere. It is possible to have seamless fabric of electronic connection with the help of electronic devices. The data which transmitted ceaselessly through electronic media which provides more assurance on cryptography to secure the data and communication. AES algorithm design is Implemented in VHDL and Simulated and Synthesized in Integrated Environment synthesis Xilinx 14.2 version software, then after actual result of AES Operation is validated on hardware in the form of Spartan 6 FPGA. From the work completed in this paper it is observed that AES Algorithm which designed and Implemented with less FPGA Hardware, Less Power consumption and Better Throughput of the Cryptosystem. Hence AES Algorithm which implemented on Spartan-6 FPGA can Give the possibility of portability, applications Compatibility and Improvement of security levels.KeywordsCryptographyInternet of thingsArtificial intelligenceFPGABlock cipher

With the development of information and communication technology, block cipher algorithm represented by AES algorithm has been used more and more widely. This design optimizes the hardware implementation of AES algorithm, mainly including: using T lookup table to realize multiple operations in round unit, ameliorating the T lookup table by using fixed value masking to improve the safety, designing a structure of inner-round loop structure and completely expanded structure, and using ISE to synthesize the AES algorithm module on Virtex-6 platform. As a result of experiment, the inner-round loop structure takes up 410slices+136BRAM, and the completely expanded structure takes up 2492slices+732 BRAM. The consumption of slices increases by only 7%-10%, and can achieve 51.2Gbps throughput under 400MHz clock. Finally, the security analysis and DPA experiments show that the fixed value masking scheme in this design improved the security of AES algorithm, and can resist SODPA.

Markov random field models provide a robust formulation for the stereo vision problem of inferring three-dimensional scene geometry from two images taken from different viewpoints. One of the most advanced algorithms for solving the associated energy minimization problem in the formulation is belief propagation (BP). Although BP provides very accurate results in solving stereo vision problems, the high computational cost of the algorithm hinders it from real-time applications. In recent years, multicore architectures have been widely adopted in various industrial application domains. The high computing power of multicore processors provides new opportunities to implement stereo vision algorithms. This article examines and extracts the parallelisms in the BP method for stereo vision on multicore processors. This article shows that parallelism of the algorithm can be efficiently utilized on multicore processors. The results show that parallelization on multicore processors provides a speedup for the BP algorithm of almost 15 times compared to the single-processor implementation on the PPE of the Cell BE. The experimental results also indicate that a frame rate of 6.5 frames/second is possible when implementing the parallelized BP algorithm on the multicore processor of Cell BE with one PPE and six SPEs.