In-Mold Electronics: An Additive Manufacturing Approach for Integrated, Robust and 3D Electronics

In implantable medical device applications, quality and reliability are critical aspects of the product. There are some unique mechanical and electrical challenges to the silver filled isotropic electrically conductive adhesive (ECA) used in these devices. The mechanical challenge is the result of the very complicated system design which involves a wide variety of integrated circuits directly bonded and over-molded onto the double-sided printed wiring board (PCB). Only a very small percentage of ECAs are capable of meeting the mechanical strength requirements for this application. These mechanically acceptable ECAs must also be thoroughly studied to ensure that a strict resistance stability requirement can be met. It is imperative to fully understand the fundamentals of the ECA material chemistry and performance relationship before it can be used in medical applications. A series of studied results will be presented in this paper. The system design challenge on ECA formulation is presented. The numerical and experimental study results on PCB design and its impact on bond pad-adhesive delamination are reported. The electrical performance of epoxy-based and acrylate-based conductive adhesives was comparatively studied. The device level critical electrical performance of conductive adhesives was found not to be correlated to bulk resistivity of cured ECA, but significantly correlated to the interfacial resistance between the cured adhesive and bond pad. Unfolding the atomic level phenomenon occurring at this interface during adhesive curing and the device burn-in process is one of the main focuses of this paper. The fundamental atomic and molecular level mechanism of the assembly process and the material chemistry impact on resistance stability will be discussed. The mechanism includes how the conductive path was formed on the adhesive and gold pad interface during adhesive cure and how the interface evolves during the burn-in process. Also discussed are ingredients in the adhesive formulation that may impact the resistance instability, and the solution space for stable resistance.

PurposeThe purpose of this paper is to present a hybrid manufacturing system that integrates stereolithography (SL) and direct print (DP) technologies to fabricate three‐dimensional (3D) structures with embedded electronic circuits. A detailed process was developed that enables fabrication of monolithic 3D packages with electronics without removal from the hybrid SL/DP machine during the process. Successful devices are demonstrated consisting of simple 555 timer circuits designed and fabricated in 2D (single layer of routing) and 3D (multiple layers of routing and component placement).Design/methodology/approachA hybrid SL/DP system was designed and developed using a 3D Systems SL 250/50 machine and an nScrypt micro‐dispensing pump integrated within the SL machine through orthogonally‐aligned linear translation stages. A corresponding manufacturing process was also developed using this system to fabricate 2D and 3D monolithic structures with embedded electronic circuits. The process involved part design, process planning, integrated manufacturing (including multiple starts and stops of both SL and DP and multiple intermediate processes), and post‐processing. SL provided substrate/mechanical structure manufacturing while interconnections were achieved using DP of conductive inks. Simple functional demonstrations involving 2D and 3D circuit designs were accomplished.FindingsThe 3D micro‐dispensing DP system provided control over conductive trace deposition and combined with the manufacturing flexibility of the SL machine enabled the fabrication of monolithic 3D electronic structures. To fabricate a 3D electronic device within the hybrid SL/DP machine, a process was developed that required multiple starts and stops of the SL process, removal of uncured resin from the SL substrate, insertion of active and passive electronic components, and DP and laser curing of the conductive traces. Using this process, the hybrid SL/DP technology was capable of successfully fabricating, without removal from the machine during fabrication, functional 2D and 3D 555 timer circuits packaged within SL substrates.Research limitations/implicationsResults indicated that fabrication of 3D embedded electronic systems is possible using the hybrid SL/DP machine. A complete manufacturing process was developed to fabricate complex, monolithic 3D structures with electronics in a single set‐up, advancing the capabilities of additive manufacturing (AM) technologies. Although the process does not require removal of the structure from the machine during fabrication, many of the current sub‐processes are manual. As a result, further research and development on automation and optimization of many of the sub‐processes are required to enhance the overall manufacturing process.Practical implicationsA new methodology is presented for manufacturing non‐traditional electronic systems in arbitrary form, while achieving miniaturization and enabling rugged structure. Advanced applications are demonstrated using a semi‐automated approach to SL/DP integration. Opportunities exist to fully automate the hybrid SL/DP machine and optimize the manufacturing process for enhancing the commercial appeal for fabricating complex systems.Originality/valueThis work broadly demonstrates what can be achieved by integrating multiple AM technologies together for fabricating unique devices and more specifically demonstrates a hybrid SL/DP machine that can produce 3D monolithic structures with embedded electronics and printed interconnects.

Hybrid Wafer-Level Packaging for RF-MEMS and Optoelectronic Applications

The effect of annealing on the morphologies and conductivities of sub-micrometer sized nickel particles used for electrically conductive adhesive

Three-dimensional (3D) electronic systems with their potential for enhanced functionalities often require complex fabrication processes. This paper presents a water-based, stimuli-responsive approach for creating self-assembled 3D electronic systems, particularly suited for biorelated applications. We utilize laser scribing to programmatically shape a water-responsive bilayer, resulting in smart 3D electronic substrates. Control over the deformation direction, actuation time, and surface curvature of rolling structures is achieved by adjusting laser-scribing parameters, as validated through experiments and numerical simulations. Additionally, self-locking structures maintain the integrity of the 3D systems. This methodology enables the implementation of spiral twining electrodes for electrophysiological signal monitoring in plants. Furthermore, the integration of self-rolling electrodes onto peripheral nerves in a rodent model allows for stimulation and recording of in vivo neural activities with excellent biocompatibility. These innovations provide viable paths to next-generation 3D biointegrated electronic systems for life science studies and medical applications.

The part of electronics packaging is steadily forced to adapt the requirements of the microelectronic industry. For future electronics application such needs will be: 1) steady miniaturisation of the electronic devices 2) high pin count up to 5000 i / o per device 3) pitches down to 20 mum 4) higher current density per devices 5) higher thermal dissipation loss This is only a small extract of the challenges facing the electronics packaging industry in the future. The aim and duty for electronics packaging is to realize a reliable package for future electronics. Commonplace materials for joining elements like solder are not able to solve these requirements. For example in [1] the authors describe that future IC's operating at high frequencies of 10-28 GHz, signal bandwidths of 20 Gbps and lower supply voltages require an estimated maximum of R (< 10 mOhm), L (<5-10pH) and C (<5-10 fF).[l] Current joining elements can not meet these requirements. To solve these problems the electronics packaging industry researches technologies and materials of the nanotechnology. Especially researches concerning new materials for electronics packaging rise up since the last three years. One of the most researched new materials are Carbon Nanotubes (CNT). Carbon Nanotubes have superior mechanical, electrical and thermal properties. Due to these properties CNT are considered as promising candidates in packaging technology. The most interesting field of application is the use of the Carbon Nanotubes as filler in electrical conductive adhesives. The aim is to improve the performance of conductive adhesives in comparison to common products. This study deals with characterization of carbon nanotube / epoxy adhesives in electronics packaging. For this study we optimize the CNT - adhesive system by modification of the CNT, use of different dispersion technologies and under variation of the epoxy matrix. The resulting adhesives are characterized by measuring their viscosity, mechanical strength and their thermal and electrical conductivity. For all studies Multi Wall Nanotubes were used which can be purchased at a reasonable price. For modification of the CNT they can be treated by low pressure plasma (cvd), UV / ozone treatment or modifiedchemically in solution to achieve a higher polarity resulting in a better dispersibility. Also bonding to the polymer matrix is improved. Success of the processes is studied by XPS and REM. For dispersion technology ultrasonic bath, speed mixing and/or treatment with a roll calander can be used. The polymer matrix is also varied in order to achieve an appropriate viscosity at the CNT-content of interest that enables good results in screen printing. Also CNT-polymer interaction can be adapted by varying polarity of the resin used. The distribution of CNT in the matrix is studied by TEM. The first investigations show that ultrasonic finger is the favourable dispersion technology to achieve well dispersed CNT. For modification of the CNT the plasma treatment came out to be efficient to give appropriate amounts of hydroxyl groups.

It is difficult for children to build electronic building blocks. In order to facilitate users to build building blocks, this paper designs and implements an electronic building block auxiliary system based on machine vision. The system uses the deep learning object detection model PP-YOLOv2 to detect the building block pictures taken by the user, obtain the location information of all the two-dimensional code in the pictures, and then decode the two-dimensional code, perform perspective transformation on the pictures, and obtain the final two-dimensional code decoding information and location information. Finally, the position of the QR code identified by the building blocks on the user's picture is crossed and compared with the position of the standard building blocks, so as to determine whether the building blocks placed by the user are correct and give the user a prompt. The system test shows that the system is not only easy to use, but also easy to maintain, and can correctly handle most of the small and medium difficulty examples in the electronic building blocks course.

Electronic manufacturing has always been on a rapid progression with the never-ending introduction of new techniques, machines and materials fuelled mainly by product demands, cost and market legislations. The recent Pb-free legislation for example has sparked off many new material developments for semiconductor packaging mainly for solder paste and mold compound. Solder pastes are used not only to mount components in System-in-Package (SIP) but also to attach dies in high power products that require maximized thermal and electrical conductivities. In short, solder pastes are still regarded as the best interconnection medium, a role which is not easily replaced by other options. The drive towards meeting the requirements of Pb-free legislation results in the replacement of the commonly use Sn/Pb solder paste to SnAgCu (SAC) solder paste. With the removal of Pb from the solder paste system, the peak temperature in the reflow profile has now increased from 240C to 260C which is now the Moisture Sensitivity Level (MSL) reflow requirement adopted by JEDEC. However, as most SAC-based solder pastes have melting temperature less than 260 C, re-melting during 3 times MSL test reflow or during board assembly is inevitable. For an SIP or multi-die type of package where the finished module will be encapsulated by mold compound, the ability of re-melting is not desirable as its liquid pressure may cause mold compound delamination. In many incidences, re-melted solder will extrude into the delaminated areas and cause electrical failures. Several other Pb-free options such as gold-based, bismuth-based pastes and even electrical conductive adhesives have been introduced in the market. This paper looks into each of these alternatives and discusses its advantages and limitations in several aspects such as materials compatibility, assembly process requirements and last but not least its reliability performances.

In this article, the use of copolymeric dispersants with an acrylic backbone and epoxy side groups for formulating carbon black (CB)‐epoxy composites are described. Six epoxy‐containing acrylic copolymer dispersants were prepared from hexyl methacrylate (HMA), poly(ethylene glycol) ethyl ether methacrylate (PEGMA), and glycidyl methacrylate via a group transfer polymerization technique. The epoxy‐containing acrylic copolymer of the highest concentration of PEGMA showed a desirable passivation effect on CB, and was found to lower the viscosity of the CB‐epoxy paste, leading to the well‐cured composite after heat treatment. The thick composite film prepared by employing the [CB/acrylic dispersant/epoxy] paste was built up on a Cu plate by a screen printing process followed by thermal curing. The dielectric properties of the 3.1 vol % CB‐filled epoxy film showed us high dielectric constant (Dk 4900) and rather low dissipation factor (Df 29%) at 1 MHz. © 2011 Wiley Periodicals, Inc. J Appl Polym Sci, 2012

IBM introduced Copper Column Grid Array (CuCGA) interconnect as the lead-free replacement for the lead-tin solder column on the Ceramic Column Grid Array (CCGA) (Figure 1). Like CCGA, CuCGA offers a high reliability packaging solution, enabling the use of ceramic chip carriers with excellent electrical and thermal performance. The move to eliminate lead in microelectronic packaging increases the complexity of processing large body size, high I/O packages. The development of manufacturable card assembly and rework processes in concert with the development of a new package interconnect structure is key to technology acceptance. Copper column interconnect (CuCGA) has been designed to meet the requirements of manufacturability, reliability, and electrical performance. Optimization of the structure for manufacturability focused on the robustness of the column during manufacturing handling and the ease of card assembly processing. The resulting card-side solder joint is key to the reliability of the interconnect. The interconnect geometry also influences electrical performance [1]. Evaluating these competing factors determined the final column design [2]. This paper focuses on the development and reliability evaluation of the CuCGA card assembly and rework processes. The goal of the process development was to adapt the successful SMT assembly process for CCGA to the developing standards for lead-free SMT processing. Successful integration of the assembly processing of the CuCGA into the developing tin-silver-copper (SnAgCu, or SAC) card assembly process posed challenges in the areas of placement, reflow, and rework. The optimization of these processes, and the proof of successful results demonstrated by reliability evaluations, will be discussed.

Photonic sintering, both with ultraviolet and near-infrared radiation, as well as thermal sintering with pressurization (autoclaving) is compared to a typical thermal curing of metal grids printed on heterojunction solar cells. For the metallization with screen printing, besides a polymer-based silver paste designed for photovoltaics, two commercially available pastes developed for the printed electronics industry have been chosen. One is optimized for autoclaving and the other for photonic sintering. With ultraviolet photonic sintering using a non-optimized process, lateral resistivities of the screen-printed contact fingers ρl of 7.6 µΩcm and contact resistivities at the metal/TCO interface ρc of 6.0-9.1 mΩcm2; are achieved. This is comparable to results reached with conventional thermal curing. Thereby, the main advantage of photonic sintering is the potential of significantly reducing the sintering time tsintering from 30 min to milliseconds. With autoclaving and near-infrared photonic sintering, lateral resistivities of 10.9 and 11.9 µΩcm are achieved, respectively.

Solution based processes such as screen printing and spray coating are established processes for fabricating organic solar cells (OSCs) on flexible polymer substrates. However, realizing a flexible solar cell on a textile substrate remains a significant challenge due to the properties of the textile itself, which can present an absorbent, rough and fibrous surface. The textile also limits processing temperatures which can reduce functional materials performance. In this work, we demonstrate an optimized fabrication approach using entirely spray coating to fabricate textile OSCs with a power conversion efficiency (PCE) of 0.4 %. An interface layer is first deposited on the standard woven textile that forms a smooth supporting layer for the subsequent spray coated functional layers. A top encapsulation layer is deposited on top of the fabricated textile OSCs, which improves the durability and life time of the OSCs is evidenced by cyclic bending test.

Cold spray-based rapid and scalable production of printed flexible electronics

With the possible future expiration of European Union (EU) Restriction of Hazardous Substances (RoHS) exemptions, allowing the use of leaded solder for the assembly of Server, Storage, and other high performance, high reliability systems, comes the need to establish new lead-free assembly processes. As the conversion to lead-free (LF) printed circuit board assembly (PCBA) processing continues to extend into high performance Server hardware platforms, new challenges have been encountered with high density, high complexity connectors. One such case involves various configurations of an SMT daughter card connector used across mid-range and high-end Server systems. This very dense, large thermal mass connector system creates significant challenges for the SMT assembly process. A basic requirement for transitioning from a leaded to a lead-free SMT solder assembly process is that connector materials be capable of surviving higher temperature exposures. At the same time, these materials must meet electronic signal integrity requirements. Furthermore, connector long-term reliability in the field environment, as simulated by accelerated thermal cycling, must not be compromised. This paper characterizes several material options for an SMT daughter card connector which is exposed to a lead-free vapor phase solder assembly process. The characterization includes base material properties, warpage during reflow, post-assembly inspections and measurements, signal integrity, and thermal fatigue performance.

During the last few years, the Solectron Technical Center has conducted a series of CSP board level manufacturing assessment studies on the self-centering effect during reflow and rework, component placement accuracy requirement, and the effects of pad design and surface finishes. Based on the results of these studies, a standard CSP assembly procedure was established. This procedure is being deployed to all Solectron manufacturing sites and is used to assess each site's CSP assembly readiness. This deployment strategy allows the corporate technology group to assess the technical capability of all Solectron sites to fulfill our commitment to enforce common process on the global basis. This paper will describe the methodology used for the deployment of the CSP assembly process. A test vehicle optimized by incorporating all the findings from the studies on pad geometry, solder volume, and surface finish was designed to assess the reliability of CSP after SMT assembly and rework processes. A series of analyses was performed on the test vehicle including the use of the mechanical deflection system designed by IBM to study the reliability of solder joints. Correlation between fatigue resistance, crack pattern, and their impact on the reliability of solder joints were also established. Stress and displacement under external thermal and mechanical fields were simulated. Finite element method was used to analyze the Von Mises stress and strain energy distributions. The impact of package standoff, die size, and DNP on the fatigue resistance and reliability of solder will be discussed.