Inline process characterization and control for robust BEOL reliability

As CMOS is being scaled down to 28nm node and beyond, BEOL process must use ultra low-K film as inter-metal dielectric (IMD) layers to reduce interconnection RC delay. Compared to low-K film, ultra-low K film (K≤2.5) is more porous, softer and more hydrophilic intrinsically, and easy to be damaged by process plasma, film stress, thermal and aqueous environments. The paper focuses mainly on the BEOL processes, such as etch PET, metallization, CMP, thermal treatment impact of ultra low-k dielectrics on reliability performance of electromigration (EM) and time-dependent dielectric breakdown (TDDB) or dielectric voltage breakdown (VBD). Some optimized BEOL processes with improved control of damage on porous low k materials could lead to an acceptable EM and TDDB performance.

This paper reviews the most encouraging process options for improving backend-of-line reliability performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Furthermore, time-dependent dielectric breakdown has to be carefully evaluated. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28nm technology nodes. In addition to electromigration and time-dependent dielectric breakdown, the impact of the various process options on stress migration performance is discussed.

TSV is the key component in fabricating 3-D ICs which can bring lower power consumption, higher integration density and shorter interconnection length. Very few works on EM and TDDB of TSV have been done. Thus, TSV macros with BEOL and backside metal were designed and tested adventurously with EM and TDDB reliability perspective. For EM, the void, however, was found at Cu/SiN interface between TSV bottom and backside metal not at TSV itself due to unexpectedly strong reliability of TSV. And also the TDDB occurred at IMD not at TSV dielectric oxide layer. As a result, the minimum level of reliability of TSV has been obtained experimentally in silicon data at least although the reliability of TSV itself has not been assessed exactly. The guide lines for making reliability macros and testing conditions are suggested also by further investigation.

As CMOS is being scaled down to 28nm node and beyond, it is necessary to reduce k value in order to improve RC delay. ULK (ultra-low k) (k<2.55) has been implemented into production from 45/40nm node. Compared with low-K film, ultra-low K film is more porous, softer and hydrophilic intrinsically. It is easy to be damaged by plasma, stress, thermal or aqueous environments. It brings more challenges for reliability improvement. This paper focuses mainly on ULK process optimization through simple key parameter optimization to improve voltage break down (VBD) and time-dependent dielectric breakdown (TDDB) and electro migration (EM) performance without scarifying RC delay.

Ultra low-k films are used in advanced technologies as dielectric interlayers in Cu interconnects. Due to its high porosity, manufacturing reliable low-k films faces many challenges. This paper discusses the reliability of time dependent dielectric breakdown (TDDB). Degradation of the TDDB lifetime can be observed when there is an abnormal I–V breakdown. Our study characterized the interaction of the breakdown leakage to the etch profile. It has shown that the etch profile weak points have impacts on the TDDB lifetime. By characterizing the Cu etching profile and establishing inline correlations to its TDDB lifetime, a new evaluation method was identified to quickly and precisely reflect the TDDB lifetime performance.

This paper will compare the reliability results of first-generation Carbon-doped low k dielectric film with a second-generation Carbon-doped film, developed to have a high mechanical strength (HMS) and improved toughness. The first-generation low k film possessed acceptable unit process results, but was found to have marginal electromigration (EM) performance due to cohesive failures that resulted in Cu extrusion at the anode end of lines. By replacing the first-generation film with the HMS film, EM test median time to fail was increased by a factor of more than two. This improvement was found to be due to increased film fracture toughness.

We studied Cu/low-k integration to test the time-dependent dielectric breakdown (TDDB) reliability of Cu interconnects. We described the TDDB lifetime dependence on SiOC damage caused by sputtering and chemical–mechanical polishing (CMP) processes. The TDDB lifetime of the structure without a cap-SiO layer was three orders of magnitude shorter than that of the structure with the cap layer. However, the film properties of cap-SiO films thinner than 30 nm have a leakage path that allows TDDB degradation to occur easily. We also confirmed that narrowing of intermediate wiring levels with metal-to-metal spacing approaching 100 nm degrades TDDB performance. Moreover, we showed the possibility that chemical attack and mechanical destruction during the polishing cause degradation of TDDB. Optimizing CMP conditions and eliminating the CMP-surface leakage path likely improve line-to-line insulating reliability, such as leakage current and TDDB, because these reliabilities are dominated by the extrinsic failure mode.

The influence of the SiN cap-layer deposition process including different pre-clean treatments on the electromigration (EM) and stressvoiding (SV) behavior of copper dual damascene metallizations has been studied. A remarkable trade-off between the EM and SV performance was revealed depending primarily on the pre-treatment before cap-layer deposition rather than the deposition process itself. On the one hand, an pre-treatment yields improved Cu/SiN-interface properties with higher electromigration failure times and activation energies (1.22-1.26 eV). However, these pre-cleans were found to provoke stressvoiding failures because of the recovery of crystal defects induced in the bulk copper during the plasma treatment. The degree of microstructural damage and hence the SV susceptibility were found to increase with the preclean intensity. In contrast, no SV risk is related to less aggressive pre-clean treatments since they influence only the copper surface. The crystal structure of the bulk remains unaffected and hence, in the absence of any crystal recovery, no vacancies are generated. However, these pre-cleans result in significantly lower EM performance with smaller failure times and activation energies (1.03-1.06 eV). The results illustrate the need to adjust the SiN cap-layer process parameters with respect to both EM and SV performance to meet the overall reliability requirements for these wear-out mechanisms at the same time.

Time-dependent dielectric breakdown (TDDB) is one of the most important reliability issues in Cu/low-k technology development. With continuous technology scalings to nanometer scales, TDDB issue is further exacerbated. In this paper, two failure mechanisms were investigated: the Ta ions migration model and the line-edge-roughness (LER) model, which is rendering the observed TDDB failure. Complimentary Raman and FTIR spectroscopy was applied to investigate the dielectric bonding characteristics. Our experimental results revealed the TDDB degradation behavior of Cu/ultra-low-k interconnects, suggesting the intrinsic degradation of the ultra-low-k dielectric. No out-diffusion of Cu ions was observed in Cu/Ta/TaN/SiCOH structures. Extensive TEM analysis further verified the migration of Ta ions from the Ta/TaN barrier bi-layer into the ultra-low-k dielectrics. Based on the LER model analysis, a comparative study in both passing and failing die elaborates that the sloped trench/via profile affected the TDDB performance.

In-line process control in microelectronics manufacturing requires real-time and non-invasive monitoring techniques. Among the different metrology techniques, scatterometry, based on the analysis of ellipsometric signatures of the light scattered by a patterned structures, is well adapted. Traditionally, the problem of defining the shape and computing the signature is dealt with modal methods and is called direct problem. On the opposite, the inverse problem allows to find the grating shape thanks to an experimental signature acquisition, and can not be solved as easily. Different classes of algorithms have been introduced (evolutionary, simplex, etc.) to address this problem, but the method of library searching seems to be the most attractive technique for industry. This technique has many advantages that will be presented in this article. However the main limitation in real-time context comes from the short data acquisition time for different wavelengths. Indeed, the lack of data leads to the method failure and several database patterns can match the experimental data. In this article, a technique for real time reconstruction of grating shape variation using dynamic scatterometry is presented. The different tools to realize this reconstruction, such as Modal Method by Fourier Expansion, regularization technique and specific software and hardware architectures are then introduced. Results issued from dynamic experiments will finally illustrate this paper.

The time dependent dielectric breakdown (TDDB) of four organo-silicate-glass (OSG) films with varying porosity (k=2.0, 2.5, 2.8 & 3.0) was investigated using metal-insulator-semiconductor (MIS) capacitors. Without any barrier, the dielectrics show lower TDDB-lifetimes under Cu ion drift conditions, where the OSG-2.8-film exhibits a better performance. Other results are that the damage caused by TaN/Ta barriers doesn't significantly change the TDDB performance and that the OSG-2.0-film showed excellent TDDB lifetimes.

Ahstract- Multi-level Metal-Oxide-Metal Capacitors (MOM) is widely utilized in CMOS process. It is an inter-digitated three dimensional multi-level finger capacitor structure formed in dual damascene copper metal layers in the Back-end-of-Line (BEOL) process. Key factors impacting the Time-dependent dielectric breakdown (TDDB) performance of MOM are identified, and results are discussed in this paper. Voltage Ramp (VRamp) analysis is used as the response of the performance of TDDB as it is well known that they are correlated to electric field acceleration parameter of the SQRT E model.

We have found that Cu-line walls located along the peripheral of the test chips improve lifetime in chip-level electromigration (EM) test and time-dependent dielectric breakdown (TDDB) test for Cu/porous-methyl-silsesquioxane (MSQ) structure. After EM test at elevated temperatures, Cu loss and extrusion are greatly suppressed in the samples with the walls. They seem to be promoted by any reactants such as moisture or oxidant penetrated from the surface on the chip side and to cause short EM lifetime. Therefore, the above layout is effective and essential in future Cu/low-k integrity.

Cu based metal trench is essential for the downscaling of interconnects for 20–10nm technologies, where it is important to optimize the materials and processing on the barrier and cap layer for a promising resistivity and electromigration (EM) performance. In order to shorten the period of process evaluation, a fast wafer-level EM characterization method is highly demanded rather than the conventional package-level EM lifetime test. In this paper, the low frequency noise measurement is proposed to investigate the EM reliability on the advanced copper interconnects. The noise expression was studied by an extensive experimental measurement. It was found that the low frequency noise measurement is a more sensitive method for studying EM degradation and can be an early indicator for EM characterization. In particular, the threshold current (I th ) and the power spectral density (PSD) is suggested to be used as a fast and useful tool for evaluating EM performance.

Two fully self-aligned via (SAV) integration schemes by metal recess approach and area-selective dielectric-on-dielectric (DoD) method are reported in this paper. A topography with enlarged diagonal distance is essential for the vias to be self-aligned. The metal recess approach encounters challenge of poor uniformity, high surface roughness, and degraded metal integrity. The DoD approach featuring an upward dielectric terrace deposited by selective-SAM-blocking method shows two orders of magnitude improvement in via-to-line time dependent dielectric breakdown (TDDB). Furthermore, this work demonstrates that high selectivity DoD can achieve industry standards of via and line resistance performance, via-chain functional yield, and metal line TDDB and electromigration (EM) reliability. In summary, the SAV by DoD is a viable approach to enable interconnect scaling beyond 3nm node.