Innovative Materials For Advanced Semiconductor Packaging

As advanced packaging continues to drive towards heterogeneous integration, new materials need to be developed to address the many challenges faced in the assembly process. This presentation will focus on innovative materials for advanced packaging, particularly for small form factor modules, including novel flux formulations for flip chip attach that are compatible with underfill and molding compound, an adhesive agent for fluxless soldering with a formic acid atmosphere, solders with various temperatures for hierarchical soldering. The technology drives toward increased functionality, better efficiency, and higher power density; advanced packaging silicon chip/die size is now bigger, with densely packed interconnect, tighter pitch, and smaller bumps. Some of the common issues we observed due to these are warpage-induced open joints from the big and thin die, flux residue removal challenges due to the tight spacings, and thermal-induced reliability issues. Novel flux formulations and adhesive agents for wafer/die bonding are needed, and interactions between the flux material and various dielectric materials on the wafer need to be better studied. The shift towards using semiconductor-grade ultra-low residue no-clean flip-chip fluxes, which eliminates the cleaning process, is one of the solutions for overcoming these challenges. Another possible solution, studied in recent years, is using a near-zero residue fluxless adhesive agent to hold the die in place while reflowing in a formic acid reflow atmosphere. The development of new solders is also a critical enabler for heterogeneous integration. If there are different reflow cycles that require a solder hierarchy, alloys with varying melting temperatures may be needed for SIP. In addition, lower melting-temperature solders can provide better warpage control, especially for thin die and substrate, as well as for heat-sensitive sensors, die, or substrate that require low-temperature processing. Alloys with enhanced reliability are also needed for certain SIP modules. In summary, proper selection and application of interconnect materials for various assembly processes is crucial to ensuring high production yield for the assembly process of advanced packaging and SIP application.

IBM introduced Copper Column Grid Array (CuCGA) interconnect as the lead-free replacement for the lead-tin solder column on the Ceramic Column Grid Array (CCGA) (Figure 1). Like CCGA, CuCGA offers a high reliability packaging solution, enabling the use of ceramic chip carriers with excellent electrical and thermal performance. The move to eliminate lead in microelectronic packaging increases the complexity of processing large body size, high I/O packages. The development of manufacturable card assembly and rework processes in concert with the development of a new package interconnect structure is key to technology acceptance. Copper column interconnect (CuCGA) has been designed to meet the requirements of manufacturability, reliability, and electrical performance. Optimization of the structure for manufacturability focused on the robustness of the column during manufacturing handling and the ease of card assembly processing. The resulting card-side solder joint is key to the reliability of the interconnect. The interconnect geometry also influences electrical performance [1]. Evaluating these competing factors determined the final column design [2]. This paper focuses on the development and reliability evaluation of the CuCGA card assembly and rework processes. The goal of the process development was to adapt the successful SMT assembly process for CCGA to the developing standards for lead-free SMT processing. Successful integration of the assembly processing of the CuCGA into the developing tin-silver-copper (SnAgCu, or SAC) card assembly process posed challenges in the areas of placement, reflow, and rework. The optimization of these processes, and the proof of successful results demonstrated by reliability evaluations, will be discussed.

The demands for increased data transmission rates and bandwidth as well as reduced signal loss are increasing while package size is getting bigger. To accommodate increasing package size and manage high frequency loss and warpage management, Glass substrates in advanced packaging are gaining momentum for heterogeneous integration of advanced semiconductor packaging. Based on Yole report in 2020, a 2.5-3 fold increase from 2019 to 2025 for the glass substrates is predicted. Glass core and Glass interposer could become a leading processing technology in advanced Panel Level Packaging (PLP). Cost effectiveness and high-frequency characteristics of glass laid strong pathways for Advanced Packaging Roadmaps. However, insertion of glass poses several challenges such as CD uniformity of Through Glass Via (TGV) etch over different aspect ratio of via sizes. Also due to the CTE mismatch between glass and metal, adhesion and stress management appears to be a huge issue for integration of TGV metallization and RDL layers. This paper presents the detail of TGV etch process with respect to different glass types, laser modification methods, and aspect ratio. Etching characterization over bath life as well as with various Design of Experiments (DOE) was performed to address the HVM challenges. Fabrication of TGV and metallization requires a good buffer layer (BL) on glass vias followed by Eless Cu deposition. Based on the types and properties of buffer layer, buffer layer serves the purpose of adhesion promotion liner (APL) as well as stress buffer layer (SBL). Additionally, Electrode less (Eless) Cu would be beneficial to provide as seed layer for conformal or full TGV metallization. Hence, a closer look into the development of Through Glass Via (TGV) processing, Adhesion promotion layer (APL), and Eless Cu techniques are discussed in this paper. A Wet process system has been developed to enable the TGV processing, Adhesion promotion, and Eless Cu for different types of glass substrates. Cross sectional and chemical analyses were done to validate the studies and the data were used to develop the glass etching, APL/SBL, and Eless Cu. Simulation and experimental data indicates that this approach is feasible to address glass processing and stress management challenges.

The rapid advancement of artificial intelligence (AI) has propelled the demand for high-performance computing (HPC) systems capable of handling vast amounts of data. This necessitates improvements in data processing speed within system-on-chip (SoC) units and efficient data transmission between SoC and high-bandwidth memory (HBM). Advanced packaging solutions, particularly the silicon interposer and organic interposer, have emerged to address these challenges. This article delves into the thermo-mechanical performance of 2.5-D packages with an organic interposer, focusing on warpage management during fabrication and stress analysis induced by coefficient of thermal expansion (CTE) mismatches. The study employs finite element analysis (FEA) modeling to evaluate the impact of various factors on warpage behavior and stress levels. Parametric studies on material selection and interposer geometric design reveal crucial insights. Specifically, reducing bridge die and redistribution layer (RDL) thickness mitigates warpage at the controlled collapse chip connection (C4) level, albeit with adverse effects on BGA level warpage. Material selection significantly influences warpage behavior. Organic materials with higher CTE reduce the mismatch between the interposer and the substrate but it is adverse for the interconnection between chiplets and interposer. Moreover, stress analysis indicates the organic interposer’s effectiveness in reducing interconnection stress compared to silicon interposers. This research contributes valuable insights into the design and optimization of advanced packages with bridges embedded in organic interposers, providing guidelines for material selection and geometric design to enhance reliability and functionality. The findings facilitate the development of advanced packaging solutions capable of meeting the demands of AI-driven applications in challenging operational environments.

The line between packaging and silicon interconnect technology is blurring due to a reduction in package interconnect dimensions, which drives an increase in image resolution requirements. It is becoming more difficult to localize and image defects and structures throughout the packaging life cycle, from materials selection, through package and silicon design co-optimization, development, production, and field failure diagnostics. Characterization and failure analysis (FA) solutions must provide fast results for rapid development of packages meeting the required electrical, mechanical and reliability specifications with high yield and quality. Heterogeneous integration and complex packages containing multiple die drive new approaches to rapidly characterize structures, defects and processes. This paper presents new artificial intelligence (AI) developments in 3D X-ray microscopy (XRM) for non-destructive submicron-resolution imaging of packages. It also introduces the latest developments in focused ion beam (FIB) microscopes adapted with an integrated fs-laser for precise and fast analysis of deeply buried features in advanced packages.

In this work, the assembly process development of a high density fine pitch multi-chip package with first and second level lead-free interconnects on a build-up substrate printed with polymer thick film (PTF) resistors is presented. Material selection and process parameters are discussed and addressed in this manuscript. Various assembly process and observations during the high density fine pitch flip-chip assembly process are also discussed in the manuscript, including underfill and package reliability issues.

In system on flex (SOF) packages with high density I/O's, larger die size, and fine pitch, the mismatch of material properties between the silicon die, underfill (encapsulant) and flexible substrate induces concentrated stress field around the bonded areas (Bumps & traces) during assembly process. The concentrated stresses result in delamination on various interfaces involving a range of length scales from hundreds of nanometers to millimeters; this delamination can be seen as halo after cross-section SEM analysis. This delamination of underfill increases the chances of moisture absorption and potentially results in electro-chemical corrosion of the stressed area. This corrosion could affect the reliability of the package. In this paper, a detail study on which factors affecting the generation of these micro-delamination in underfill is investigated. The delamination is driven by either the adhesion failure within the substrate and underfill or by the stresses induced in the interfacial sites. We developed an extra cleaning process to remove seed-layer Cr+ to avoid adhesion failure due to contamination of flex. Strength of underfill to avoid failure under shear stress depending upon various properties is analyzed. It shows that filler material have more strength that non-filler materials but at cost of flow rate and voids. It was observed after TCT and button shear test that underfill with higher tensile strength could absorb more stresses. Effect of peak temperature during assembly process was studied; this showed that underfill delamination across the interfacial sites increases with increase in temperature. So assembly process development with lower temperature is more beneficial for high reliability of SOF packages.

The Semiconductor Industry has been relying for decades on Moore’s Law as the path to increase functionally and transistor count while lowering the cost/node. As we are pushing the limits we are facing a reality where going to smaller geometries is no longer offering the benefits of cost reduction, and the applications that can benefit from < 20nm process is limited to specific applications that can command high ASPs. We are at an inflection point where Advanced Packaging can play a more significant role to support further integration and cost reduction, leveraging existing Assembly technology and Foundry resources augmented by innovative initiatives from leading OSAT, Foundry and IDM’s. Traditionally, assembly equipment followed the technology developed for the foundries, especially when it comes to WLP where most of the equipment was developed to support the Wafer form factor. Breaking this wafer form factor requires development of new tools that can support reconstruction of wafers taking the KGD and “converting” them into a larger carrier that can be then processed in parallel through the entire assembly process. The lowest common denominator dictates the limit for the entire assembly line, thus the drive is to enable the largest possible panel that can be supported in all steps of the assembly process. In this Paper, Universal instruments will present a revolutionary solution enabling the highest accuracy for the largest work area without compromising UPH offering the best cost/performance and economies of scale that are essential for deployment in HVM.

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm has presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. And in the very cost sensitive advanced packaging arena, Outsourced Semiconductor Assembly and Test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from the backend processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, where the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with Infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist is then stripped and cleaned. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2um is readily achievable, with no impact on system throughput.

The microelectronic packaging field is moving into the third dimension for miniaturization, low power consumption, and better performance. In this paper, we present a double-sided flip-chip organic substrate with a memory controller on one side of the package, and 3D stacked disaggregated memory chips on the other side of the package. This design allows the controller to interface with the DRAM stack directly through the substrate providing the shortest possible interconnect path, and thus achieving the fastest signaling speed. However, this double-sided flip chip on organic substrate also causes yield, assembly, test, and reliability challenges. In order to optimize the assembly process, a sequential 3D finite-element model was developed to simulate the package assembly process. In these simulations, various assembly process sequences were simulated with different conditions and materials. In addition, a probing test model was also built to study the connectivity of the Land Grid Array (LGA) pin array with the PCB sockets. Results show that the careful selection of assembly steps and package materials are crucial for the successful package assembly and also important for the probing test.

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore’s law, and the ability to produce FinFETs below 10nm have presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore’s law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. In this very cost sensitive advanced packaging arena, outsourced semiconductor assembly and test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from back-end processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, that the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist stripped, and the lithography layer reworked. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper-based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system’s regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2μm is readily achievable, with no impact on system throughput.

Current technology trend demands not only for high efficiency but also for portable devices, devices which can be carried and access anywhere and everywhere. This continues drives semiconductor's package towards miniaturization. One way is by placing active circuitry underneath the bond pads, this will reduce the die size, hence achieve lower cost per chip. This technology has led to the development of a more robust top metal that can withstand the high ultrasonic energy being applied in the bond pad. The use of thick copper power metallization in package design had shown significant benefits over the conventional aluminum top metal. Copper power metallization is a stack layer of thick copper (10um), nickel (2.0um) and gold (0.5um) plated over the top passivation layer. These prominently improve the overall device electrical performance with higher efficiency and lower Rds(on) by offering metallization with lower resistance and enables die size reduction of 10∼25% and provides flexibility which allows assembly of thicker bonding wires for high power applications. In copper power metallization, it helps in bondability and improves structural robustness especially with copper wire for underlying circuitry during the process. This paper presents the unique structure of this pad metallization, the challenges from die design phase and also looked at potential issues concerning passivation cracks and pad corrosions. This paper will also tackle how a stack layer of CuNiAu mitigates issues which are commonly encountered with Cu-Al bonding system (aluminum splash out issue, pad cratering and galvanic corrosion). The overall component interface integrity for this new metallization is unknown to us. Detail simulations were carried out to understand the system stress generated between the copper power pad and silicon (Si) die which affect the passivation integrity as well. Detail characterizations will be discussed to understand the ratcheting mechanism and its resolution. Assessment on package integrity with Moisture Level Sensitive (MSL1) condition was done to ensure it is well integrated with currently assembly process and material used with no delamination found.

The advent of electric aircraft heralds a transformative era in aviation, offering a sustainable alternative to conventional aircraft that significantly contribute to carbon emissions. This paper discusses the application of advanced materials in overcoming the technical hurdles associated with electric propulsion systems, focusing on their application in airframe construction, electrical conductors, thermal management, and battery technology to enhance the performance and sustainability of electric aircraft. Advanced composites like carbon fiber reinforced polymer (CFRP) are explored for their potential to reduce aircraft weight and improve mechanical properties. The paper also addresses the challenges of thermal management in electric propulsion systems, highlighting the use of phase change materials (PCMs) and advanced ceramics for efficient heat dissipation. Furthermore, the exploration of high-energy-density cathode materials, innovative anode materials, and solid-state electrolytes is discussed in the context of developing lightweight, high-capacity batteries for electric aircraft. Despite the promising advancements in material science and the potential benefits of electric aviation, the paper acknowledges the existing challenges, including the high cost of advanced materials, the need for improved energy storage solutions, and the environmental impact of material production.

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance.

With the ever increasing complexity of today's IC packaging designs and new packaging technologies of tomorrow, coupled with the increasingly global nature of design and manufacturing / assembly, traditional 2-D EDA packaging tools and design collaboration capabilities do not have the required feature subsets nor controlled and seamless design sharing integration needed to support 3-D design technologies. These current solutions cannot adequately meet advanced packaging's current and future needs. New generation 3-D EDA tools and design collaboration systems that integrate 3-D design and global data collaboration are required to meet these expanding technologies. The conventional 2-D IC package design process flow begins with top-down design and layout, and utilize software tools that only have the ability to verify 2-D design rule checks (DRC). These limited rules, while sufficient for lead frame, single tier Ball Grid Array (BGA), and other single level package types, do not take into consideration advanced System in Package (SiP) stacked die configurations with multi-die advanced bond wire and other connection technologies with accompanying manufacturing variables and tolerances. The lack of tools that accurately model these 3-D manufacturing parameters result in substantial trial and error in the assembly set up process, increasingly poor yields as complexity increases, and in some cases, eventual package / substrate redesign after costly time and resources in manufacturing have already been expended. In addition, the design and manufacturing and assembly departments tend to be organizationally as well as geographically separated with little or no real data transfer or feedback between the departments. The result is evident in current package designs that are completed according to basic rules without the benefit of, nor the ability to incorporate optimal manufacturing data. These designs are completed “successfully” (from a 2-D design standpoint) and then sent to manufacturing and assembly. These “successful” designs are then evaluated from a manufacturing and assembly viewpoint, and real world manufacturing parameters are utilized to “redesign” the assembly of the package to attempt to make the package manufacturable. The optimization of the design for manufacturing can take days or weeks to accomplish through a long process of trial and error. Many iterations of the assembly prototype are made until it is deemed manufacturable, or if not, the design is sent back to the design department for re-design. In order to increase reliability, increase yields, and decrease time to market for advanced SiP and other stacked technologies, a 3-D design collaboration system is required to integrate the design, verification, manufacturing, and assembly processes into a seamless system that is globally accessible in real time by all departments. This system must provide data access to the designer from all related departments, including engineering, simulation, manufacturing, assembly, etc. in order for the designer to be able to optimize the design for maximum performance as well as the highest yield and shortest time-to-market. This system will accurately verify 3-D assembly parameters during the design process. Manufacturing, engineering, and assembly departments will be able to input manufacturing parameters into the design, thereby eliminating much of the trial and error prone in the package design and assembly process today, and the design can be shared by multiple users and departments for true collaboration. This paper explains the role and manufacturing benefits of a 3-D package design and global data collaboration system.