Innovative Thermal Approaches to Fault Isolation in Three-Dimensional Semiconductor Structures

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.

Novel concepts of designs for diagnosability and reliability are defined and developed. A diagnosable design of VLSI system is presented, in which fault isolation is realized by minimal additional hardware instead of traditional software diagnostic procedures such that the computation space and time for fault isolation are saved. The presented fault-tolerant design uses online fault detection and isolation techniques, yields higher reliability with minimized hardware overhead of no more than 125% as opposed to over 200% in classical redundancy fault-tolerant designs. Using this scheme, the ability to isolate intermittent faults is a significant improvement over existing fault isolation methods because faults could be isolated right after they are detected. >

Failure analysis (FA) could provide timely feedback to process optimization and solution paths for system failures; thus, it is critical for the development of advanced driver assistance systems (ADAS). In this chapter, failure analysis flows starting from systems or boards until components or packages and dice are introduced. Electrical fault isolation (FI) techniques designed to locate subtle defects inside complicated semiconductor devices are reviewed. Physical failure analysis approaches adopted to provide artifact free nanometer scale analysis are discussed. Material analysis methods assisting in thorough root cause investigation are presented. Non-destructive and high-resolution imaging tools with the potential of significantly shortening failure analysis through put time are demonstrated. Case studies are used to illustrate strategies and methodologies in ADAS failure analysis.

Fault Detection and Isolation (FDI) techniques have captured extensive interest and attention in modern autonomous systems; in particular, they are of foremost importance in space applications, due to their scientific relevance, cost and current inability of doing on-orbit maintenance of space systems. In this scenario, FDI strategies are required to counteract possible failure events that, if not properly handled, can reduce system performance or compromise the realization of the mission objectives. In this paper, a model-based FDI strategy is implemented onboard a satellite equipped with a very large mesh reflector on which a distributed network of smart actuators/sensors is mounted to actively counteract undesired elastic vibrations. In particular, the detection and isolation of a possible piezo-actuator failure occurring in the Active Vibration Control (AVC) system of the antenna is addressed by a bank of Unknown Input Observers (UIOs). The design of the proposed UIOs is derived by solving a Linear Matrix Inequality (LMI) problem, which provides the conditions for their existence, and it is based on the linearized 3D state-space model of the controlled spacecraft, under the assumption that all the uncertainties, exogenous disturbances and measurement noises are neglected. Furthermore, pole assignment in the sense of D-stability is integrated in the standard formulation of the UIO to guarantee an adequate transient behaviour of the observers. Finally, an extensive Monte Carlo simulation campaign is conducted to assess the effectiveness of the proposed FDI architecture and its robustness against modelling uncertainties and measurement noise.

Application of data reconciliation for fault detection and isolation of in-core self-powered neutron detectors using iterative principal component test

Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

93

This chapter describes the adoption and application of finite element analysis (FEA) during the design and failure analysis of medical devices. FEA has been an important product development tool in the medical device industry, by allowing designers to explore various design options quickly and quantitatively. The chapter discusses some of the key steps and important considerations in applying the finite element method to the design and failure analysis of devices, and provides an example on how these steps are implemented in a nitinol inferior vena cava filter (IVCF) wire frame design and validation.

Quantifying activation energy (Ea) is essential for evaluating the thermal reliability of NAND flash memory technologies. Conventional approaches rely on threshold voltage (Vt) shift measurements under thermal stress, which are often inaccessible in Commercial Off-The-Shelf (COTS) NAND devices. In this work, we present a digital probing method to estimate activation energy using fail bit counts (λFBC), enabling reliability evaluation without requiring direct V. access. The proposed technique tracks bit-flip events caused by charge loss or injection at elevated temperatures (40∘C to 120 ∘C) and computes the median fail bit count (VFBC) over time. Using the Arrhenius relationship, we extract activation energies of 1.09 eV and 0.76 eV for 2D and 3D multi-level cell (MLC) NAND flash memory, respectively. The results highlight the architectural differences in degradation behavior and demonstrate the efficacy of.FBC as a digital reliability metric. Comparative analysis with existing threshold voltage-based methods validates the accuracy of the proposed technique. This work establishes a non-invasive and scalable method for activation energy extraction, facilitating comprehensive reliability characterization across modern NAND flash technologies.

Fault Detection and Isolation of an Aircraft Using Set-Valued Observers

An Unknown Input Kalman Filter (UIKF) based Component Fault Detection and Isolation (CFDI) technique for a dynamical system, affected by both plant and measurement noise, is presented. The Fault Detection and Isolation (FDI) algorithm, which consists of two steps, is developed with the assumption that the fault occurs in a single component of the system. In step 1, the detection of the fault and the isolation of the faulty region are achieved. In the next step, the faulty parameter is isolated from the faulty region. The method is applied on a road vehicle model to show the effectiveness of the algorithm.

Through-focus scanning optical microscopy (TSOM) is a model-based optical metrology method that involves the scanning of a target through the focus of an optical microscope. Nanometer scale sensitive information is then extracted by matching the target TSOM data/image to reference TSOM data/images that are either experimentally or computationally collected. The nanometer sensitivity was previously confirmed by several theoretical and optical implementations. However, these studies all involved application to wafer patterns on the top surface. The present study extends the TSOM method to subsurface defect detection and classification without destruction, which becomes extremely important due to increasingly widely employed 3D semiconductor technologies. First, we apply a near-infrared (NIR) beam as illumination light in order to allow defect identification over the entire device depth. In addition, we adopt a model-less TSOM approach since the construction of a TSOM reference database for 3D pattern structures such as 3D NAND flash memory is hardly practical. We therefore employ a comparative TSOM method in which a TSOM data cube/image is compared with an image of an adjacent die or that of a “golden” die known to be defect free. We report the results of the first application of this method to an Intel 3D NAND flash and show that substantial subsurface defects are detected and classified.

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

This paper analyzes the through-put time and output of fault isolation and failure analysis (FI/FA) flows on state-of-the-art microprocessors. An average reduction in through-put time of 40% was demonstrated with a shortened FI/FA flow while still maintaining a high success rate. The direct FA/nano-probing flow which was utilized by up to around 90% of the fail cases omitted the optical fault isolation step and instead expanded the use of plasma FIB, nano-probing and electrical isolation techniques (such as diagnosis tools). The end result is shorter through-put time and higher FI/FA volume which is important in order to achieve a faster production ramp. In the paper two cases studies are presented to demonstrate the new efficient FI/FA techniques.

Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.