Input Locality and Hardness Amplification

With the growing availability of experimental loophole-free Bell tests1–5, it has become possible to implement a new class of device-independent random number generators whose output can be certified6,7 to be uniformly random without requiring a detailed model of the quantum devices used8–10. However, all these experiments require many input bits to certify a small number of output bits, and it is an outstanding challenge to develop a system that generates more randomness than is consumed. Here we devise a device-independent spot-checking protocol that consumes only uniform bits without requiring any additional bits with a specific bias. Implemented with a photonic loophole-free Bell test, we can produce 24% more certified output bits (1,181,264,237) than consumed input bits (953,301,640). The experiment ran for 91.0 h, creating randomness at an average rate of 3,606 bits s–1 with a soundness error bounded by 5.7 × 10−7 in the presence of classical side information. Our system allows for greater trust in public sources of randomness, such as randomness beacons11, and may one day enable high-quality private sources of randomness as the device footprint shrinks. Device-independent randomness expansion is demonstrated in an experiment that is secure in the presence of a classical eavesdropper who does not share any entanglement with the setup.

We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.

The strict avalanche criterion was introduced by Webster and Tavares [] in order to combine the ideas of completeness and the avalanche effect. A cryptographic transformation is complete if each output bit depends on all the input bits, and it exhibits the avalanche effect if an average of one half of the output bits change whenever a single input bit is complemented. To fulfil the strict avalanche criterion, each output bit should change with probability one half whenever a single input bit is complemented. This means, in particular, that there is no good lower order (fewer bits) approximation to the function. This is clearly a desirable cryptographic property since such an approximation would enable a corresponding reduction in the amount of work needed for an exhaustive search.

In this paper, we propose a reversible quantum 2n-to-n BCD priority encoder circuit, where n is the number of output bits. The proposed design of the 2n-to-n BCD priority encoder circuit shows that it is composed of quantum circuits for OR operation and quantum NOT gates. We present an algorithm to construct a minimized quantum 2n-to-n BCD priority encoder circuit. A technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. Our circuit performs better than the existing ones in terms of quantum gates, delays, garbage outputs, constant inputs, quantum gate calculation complexity, area and power, e.g., the proposed quantum 8-to-3 BCD priority encoder circuit improves 41.25% on the number of quantum gates, 46.05% on delays, 48% on garbage outputs, 60% on constant inputs and 41.25% on area and power than the existing circuit. We also simulate the proposed quantum BCD priority encoder circuit using Microwind DSCH 2.7 which shows the functional correctness of the circuit.

We propose a resolution enhancement scheme using optical I/O multiperiod transfer functions of NOLMs for ultrafast low-resolution electrical A/D converters (ADCs). This scheme can provide an 8-bit ADC with the effective-number-of-bits of 7.86 bit by combining 8-period optical transfer functions and three 5-bit electrical ADCs. We investigate the performance of ADC about effective resolution, the nonlinear error and missing code due to the resolution of low-resolution ADCs and the number of output bits of the resolution-enhanced ADC.

Quantum technology application is a rapidly developing discipline in future-generation research. It has grown its appeal due to several unique aspects which cannot be encountered in classical domains. Quantum properties can be used to create powerful and effective technology. The processing capability of a quantum computer is triggered by managing quantum particles in a quantum computer, which improves transformation in many domains. Quantum logic operations have the significant benefit of being reversible. Unlike classical irreversible processing, quantum logic gates are reversible and unitary, allowing input bits to be recovered via a one-to-one connection between input and output bits. In QCADesigner, as well as in the Quantum environment, different reversible logic gates may be constructed. Some other promising features include Superposition (Quantum Parallelism), Entanglement, etc. This study uses IBM quantum to create the QCA-based Majority voter gate.

This paper considers the basic $\mathcal{PULL}$ model of communication, in which in each round, each agent extracts information from few randomly chosen agents. We seek to identify the smallest amount of information revealed in each interaction (message size) that nevertheless allows for efficient and robust computations of fundamental information dissemination tasks. We focus on the Majority Bit Dissemination problem that considers a population of $n$ agents, with a designated subset of source agents. Each source agent holds an input bit and each agent holds an output bit. The goal is to let all agents converge their output bits on the most frequent input bit of the sources (the majority bit). Note that the particular case of a single source agent corresponds to the classical problem of Broadcast. We concentrate on the severe fault-tolerant context of self-stabilization, in which a correct configuration must be reached eventually, despite all agents starting the execution with arbitrary initial states. We first design a general compiler which can essentially transform any self-stabilizing algorithm with a certain property that uses $\ell$-bits messages to one that uses only $\log \ell$-bits messages, while paying only a small penalty in the running time. By applying this compiler recursively we then obtain a self-stabilizing Clock Synchronization protocol, in which agents synchronize their clocks modulo some given integer $T$, within $\tilde O(\log n\log T)$ rounds w.h.p., and using messages that contain $3$ bits only. We then employ the new Clock Synchronization tool to obtain a self-stabilizing Majority Bit Dissemination protocol which converges in $\tilde O(\log n)$ time, w.h.p., on every initial configuration, provided that the ratio of sources supporting the minority opinion is bounded away from half. Moreover, this protocol also uses only 3 bits per interaction.

This work presents the coder and decoder of block mBnB of the type 1B2B or Manchester. In the coder 1B2B each block/word of 1 input bit is coded in the block / word of 2 output bits. In the decoder 1B2B happen the inverse, each block of 2 input bits is newly converted in the original block of 1 output bit. The coder injects in the transmission line a number of 1’s exactly equal to the number of 0’s, what guarantees a DC constant component and maximizes the transitions number. The objective is to implement the pair coder and decoder 1B2B so that it improves the transmission quality and increases the information security. Keywords: Block codes, Digital systems, Transmission lines

The authors theoretically demonstrate the implementation of a low-power 4-state universal logic gate (NOR) using a linear array of three dipole-coupled magnetostrictive-piezoelectric multiferroic nanomagnets (e.g. Ni/PZT) with biaxial magnetocrystalline anisotropy. The two peripheral nanomagnets in the array encode the 4-state input bits in their magnetization orientations and the central nanomagnet's magnetization orientation represents the output bit. Numerical simulations are performed to confirm that the 4-state output bit is the Boolean NOR function of the two 4-state inputs bits when the array reaches its ground state. A voltage pulse alternating between −0.2 and +0.2 V, applied to the piezoelectric layer of the central nanomagnet, generates alternating tensile and compressive stress in its magnetostrictive layer. This drives the array to the correct ground state where dipole interaction between the magnets ensures that the output is the NOR function of the input. For the system considered, the gate operation is executed while dissipating only ∼33 000 kT (0.138 fJ) of energy.

Multiplicative complexity of vector valued Boolean functions

Non-local games are widely studied as a model to investigate the properties of quantum mechanics as opposed to classical mechanics. In this paper, we consider a subset of non-local games: symmetric XOR games of n players with 0-1 valued questions. For this class of games, each player receives an input bit and responds with an output bit without communicating to the other players. The winning condition only depends on XOR of output bits and is constant w.r.t. permutation of players. We prove that for almost any n-player symmetric XOR game the entangled value of the game is Theta((sqrt(ln(n)))/(n^{1/4})) adapting an old result by Salem and Zygmund on the asymptotics of random trigonometric polynomials. Consequently, we show that the classical-quantum gap is Theta(sqrt(ln(n))) for almost any symmetric XOR game.

Injective one-way trapdoor functions are one of the most fundamental cryptographic primitives. In this work we show how to derandomize lossy encryption (with long messages) to obtain lossy trapdoor functions, and hence injective one-way trapdoor functions.Bellare, Halevi, Sahai and Vadhan (CRYPTO ’98) showed that if Enc is an IND-CPA secure cryptosystem, and H is a random oracle, then x ↦ Enc(x,H(x)) is an injective trapdoor function. In this work, we show that if Enc is a lossy encryption with messages at least 1-bit longer than randomness, and h is a pairwise independent hash function, then x ↦ Enc(x,h(x)) is a lossy trapdoor function, and hence also an injective trapdoor function.The works of Peikert, Vaikuntanathan and Waters and Hemenway, Libert, Ostrovsky and Vergnaud showed that statistically-hiding 2-round Oblivious Transfer (OT) is equivalent to Lossy Encryption. In their construction, if the sender randomness is shorter than the message in the OT, it will also be shorter than the message in the lossy encryption. This gives an alternate interpretation of our main result. In this language, we show that any 2-message statistically sender-private semi-honest oblivious transfer (OT) for strings longer than the sender randomness implies the existence of injective one-way trapdoor functions. This is in contrast to the black box separation of injective trapdoor functions from many common cryptographic protocols, e.g. IND-CCA encryption.

4-bit Linear Relations play an important role in Cryptanalysis of 4-bit Bijective S-Boxes. Count of existence of all 4-bit Linear Relations, for all of 16 input and output 4-bit bit patterns of 4-bit Bijective S-Boxes said as S-Boxes has been reported in Linear Cryptanalysis of 4-bit S-Boxes. In this paper a brief review of this cryptanalytic method for 4-bit S-Boxes has been introduced in a very lucid and conceptual manner. A new Analysis to search for the existing Linear Approximations among the input Boolean Functions (BFs) and output BFs of a particular 4-bit S-Box has also been introduced in this paper. The search is limited to find the existing Linear Relations or Approximations in the contrary to count the number existence among all 16 4-bit input and output bit patterns for all possible linear approximations.

In this paper we study the second preimage resistance of Hamsi-256, a second round SHA-3 candidate. We show that it is possible to find affine equations between some input bits and some output bits on the 3-round compression function. This property enables an attacker to find pseudo preimages for the Hamsi-256 compression function. The pseudo preimage algorithm can be used to find second preimages of the digests of messages M with complexity 2251.3, which is lower than the best generic attacks when M is short.

We obtain the first deterministic extractors for sources generated (or sampled) by small circuits of bounded depth. Our main results are: (1) We extract k(k/nd) O(1) bits with exponentially small error from n-bit sources of min-entropy k that are generated by functions f: {0, 1} ℓ → {0, 1} n where each output bit depends on ≤ d input bits. In particular, we extract from NC 0 sources, corresponding to d = O(1). (2) We extract k(k/n 1+γ) O(1) bits with super-polynomially small error from n-bit sources of min-entropy k that are generated by poly(n)-size AC 0 circuits, for any γ> 0. As our starting point, we revisit the connection by Trevisan and Vadhan (FOCS 2000) between circuit lower bounds and extractors for sources generated by circuits. We note that such extractors (with very weak parameters) are equivalent to lower bounds for generating distributions (FOCS 2010; with Lovett, CCC 2011). Building on those bounds, we prove that the sources in (1) and (2) are (close to) a convex combination of high-entropy “bit-block ” sources. Introduced here, such sources are a special case of affine ones. As extractors for (1) and (2) one can use the extractor for low-weight affine sources by Rao (CCC 2009). Along the way, we exhibit an explicit boolean function b: {0, 1} n → {0, 1} such that poly(n)-size AC 0 circuits cannot generate the distribution (Y, b(Y)), solving a problem about the complexity of distributions. Independently, De and Watson (RANDOM 2011) obtain a result similar to (1) in the special case d = o(lg n). Supported by NSF grant CCF-0845003.