Integrated Optical Frequency Division with SiN-based Reference Cavity and Microcomb

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Low phase noise micro — mm waves are critical building blocks for future wireless communications and radar. Micro — mm waves generated by optical frequency combs via optical frequency division can have extremely low phase noise [1], but producible RF carrier frequencies are essentially limited to harmonics of the comb repetition frequency. Actively suppressing phase noise of RF oscillators is a more universal way to generate low noise arbitrary RF carrier frequencies [2, 3]. For this, electro-optic comb (EO comb) based active phase noise suppression of RF oscillators is a powerful method, compatible with referencing to micro cavities [2] and optical frequency combs [3]. In this report, we propose and demonstrate an alternative approach for active phase noise suppression by referencing to a long fiber delay, based on highly sensitive phase noise measurements as enabled via a two wavelength, delayed self-heterodyne interferometer [4].

A novel complementary ClassF 23 voltage‐controlled oscillator (VCO) is proposed. The design employs a transformer‐based tank and integrates two additional LC tanks that provide resonance at the third harmonic frequency. This harmonic superposition enables a sharp zero‐crossing region, which minimizes the effective Impulse Sensitivity Function (ISF), and consequently further improves phase noise (PN). Simulation results show that the additional third harmonic resonance contributes to a 1.4 dB reduction in phase noise compared with a standard Class F −1 oscillator. Fabricated in a 180 nm CMOS process, the prototype VCO occupies an area of 0.88 × 1 mm 2 . Measurement results show a tuning range of 4.26–4.58 GHz. The PN at 1 MHz offset is −126 dBc/Hz from the 4.26 GHz carrier frequency, with an average PN better than −120 dBc/Hz across the entire tuning range. A figure‐of‐merit (FoM) of 190.6 dBc/Hz is obtained at the 1 MHz offset. Under a 1.8 V supply voltage, the proposed design consumes a power of 6.2 mW.

Highly stable and small size local oscillators is a very important component of any remote sensing, imaging, and telecommunication systems. The key factor influencing the frequency stability is quality factor of the resonance structure. Related close-in to carrier phase noise for offset frequencies above active device corner frequency reduces at least at a rate of 20 dB/decade while offset below corner frequency increases at rate of 30 dB/decade. A new approach in realization of the electrical oscillators is to augment electrical quality factor by optical energy storage components (e.g., fiber optic delay lines and ring resonators) to enhance effective quality factor (Q) to 10^4-10^6, well beyond available electrical Q of 2000 in dielectric resonator oscillators (DRO). Moreover, stability of resonance frequency has been impacted by the environmental induced (e.g., piezo and pyro properties of material) sensitivities. In addition, micro-scale design approaches are reported using multi-mode (both semiconductor and solid state) lasers for low phase noise intermodal oscillations. Finally, forced oscillation techniques of injection locking, phase locking, and mode-locking are attractive to further stabilize electrical and optical oscillation methods. In this thesis, development of broadband stable frequency sources is reported covering both X- and K-band using forced opto-electronic oscillator technique. The broadband frequency tuning is achieved using coarse electrical tuning of YIG bandpass filter combined with fine-tuned optical transversal filter using dispersive delay component and wavelength control of a fiber laser, as optical source. Forced opto-electronic oscillation techniques of self-injection locking (SIL), self-phase locked loop (SPLL), and self-injection locked phase locked loop (SILPLL) are optimized for further frequency stabilization of a frequency synthesizer. In SILPLL application, long delay line is crucial for substantial phase noise reduction; therefore, kilometer long optical fiber delay lines have been used to construct the optical feedback since their loss is extremely low compared to electrical delay lines. Meantime, open loop gain is another key parameter to achieve low phase noise in these feedback systems, as the phase noise reduction is proportional to phase locking loop gain. The phase noise and pull-in time can be greatly reduced in SILPLL as opposed to SIL or SPLL alone. A forced oscillation of fixed frequency DRO at 10 GHz system provide -137 dBc/Hz phase noise at 10kHz offset with under 10 fs aperture jitters, while OEO based X-band and K-band synthesizers provide phase noise of -137 dBc/Hz (<10 fs jitters) and -127 dBc/Hz (<12 fs jitters) at offset 10 kHz respectively in a computer controlled 19" rack-mountable OEO systems. After realization of the desired modular frequency synthesizer, development a compact opto-electronic oscillator system is demonstrated in my PhD study. Monolithic design and testing of multi-section quantum well lasers are reported on 5x2 mm2 InP chip using a commercial foundry service (i.e., SmartPhotonics). The designed lasers consist of 4 major sections of semiconductor optical amplifier (SOA), optical phase modulator (PM) and distributed Bragg reflector (DBR) mirrors. The DBR section provides wavelength selectivity while phase section and gain medium provide output wavelength tuning. An electro-absorption modulator (EAM) is prepared for mode number control using its wavelength sensitive absorption coefficient. The experiments supported predicted performance of this multi-mode laser structure and impact of combined forced oscillation of intermodal oscillations with mode locking method to realize a frequency stabilized and tunable RF signal source. Meantime, forced technique SILPLL and optimum mode locking techniques are applied in order to achieve improved phase noise performance. The free-running inter-modal oscillation frequencies suffers from poor phase noise of -5 dBc/Hz at 1 kHz and -32 dBc/Hz at 10kHz offset around 11.54 GHz, while under forced oscillation a -58 dBc/Hz at 1 kHz offset and -98 dBc/Hz at 10 kHz offset are achieved. A frequency tuning range of 800 MHz is also measured. In mode locked laser operation, the RF beat-notes forced with SILPLL topology provides a better performance. Improved phase noise of -79 dBc/Hz at 1kHz, -110 dBc/Hz at 10 kHz is measured with under 50 fs aperture jitters, while a broadband frequency tuning from 11 GHz to 13 GHz range is measured. The tuning range is potentially to be further improved, if the shared DBR laser pair symmetry could be improved. In summary, this thesis provides the solution for building RF synthesizer using forced opto-electronic oscillator and laser beat-notes oscillation output. The experimental results are corroborated with detailed analytical and numerical modeling to optimize oscillator phase noise performance. The modular design solution shows great stability and low phase noise, while the compact monolithic design solutions are quite attractive for a smaller size. Potential for full integration of multi-mode multi-section MQW laser with optical delay lines are also presented as a logical development path towards a compact frequency synthesizer.

In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dual-core LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07–4.91 GHz, while drawing 39–59 mA from a 2.15 V power supply. The measured PN is $-$ 146.7 dBc/Hz and $-$ 163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area.

The methods to reduce phase noise of crystal oscillators are presented and analyzed in the paper. According to analysis of Leeson formula, phase noise has a direct relation with noise factor F, corner frequency f c and loaded quality factor Q L . Based on the method of reducing phase noise by improving Q L , the formula of Q L is derived by analysis of Pierce oscillator circuit and simulated by MATLAB. According to the simulation result, we can draw a conclusion that Q L is explicitly related to circuit parameters. Based on this conclusion, phase noise of a Pierce crystal oscillator is simulated and analyzed by the Agilent Advanced Design System. The simulated phase noise results are reduced by adjusting circuit parameter. A design of the prototype 120 MHz Pierce crystal oscillator is presented and the experiments are carried out. The measured near carrier frequency phase noise can achieve −100 dBc/Hz@10Hz and −132 dBc/Hz@100Hz. The simulated and experimental results show that it is feasible to design low phase noise crystal oscillator based on improving Q L .

A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from −88 to −109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from −16.8 to −34.6dBc, when operating at 2.4GHz.

Phase noise in coupled-oscillator arrays of single-ended inverter-based ring-oscillators has been analysed using a time-domain delay-based model for injection locking. This paper demonstrates a heterogeneous coupled-oscillator array (multiple frequency oscillators coupled to each other) which can decrease phase noise, with an improvement in power consumption, viz. for a 15 dB reduction in phase noise, we increase power consumption by only 12 dB. An oscillator running at 2.56 GHz coupled with an oscillator array of 36 coupled oscillators running at 1.28 GHz, was measured to have a phase noise of -103 dBc/Hz at a 1 MHz offset from the center frequency of 2.56 GHz, with a total power consumption of 3.7 mW.

We propose an ultra-low phase noise oscillator topology that works on the premise that coupling a second identical oscillator core would reduce the overall phase noise by 3 dB. For each core, a high-swing class-C oscillator is used to achieve the lowest phase noise. The realized oscillator is tunable from 4.07-4.91 GHz, drawing 39-59 mA from a 2.15 V power supply. The measured phase noise is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from 4.07 GHz carrier. This is the lowest ever reported phase noise in bulk CMOS IC. This phase noise meets GSM900 normal basestation receiver and mobile station transmitter standards, which have the toughest phase noise requirements in cellular communications.

Phase noise reduction in a CMOS LC cross coupled oscillator using a novel tail current noise second harmonic filtering technique

Carrier frequency offset (CFO) and phase noise are challenging problems in single carrier frequency division multiple access (SC-FDMA) system. In this study, the authors have studied single-carrier space frequency block coding (SC-SFBC) to reduce the peak to average power ratio (PAPR) of the multiple-input multiple-output (MIMO) SC-FDMA signal, in which Alamouti SFBC will change the signal spectrum structure, break the single-carrier property and increase PAPR. Also, the authors propose a joint algorithm to suppress the inter-carrier interference (ICI) caused by phase noise and CFO. Conventional methods are to estimate phase noise and CFO in other algorithms, which are pretty difficult and complicated to obtain accurate estimation results. Unlike the conventional works, the novelty of the authors proposed algorithm is that it directly calculates the interference components and then reconstructs the ICI matrix. Thus, it avoids the degrading interactions between phase noise and CFO estimations. The proposed algorithm exploits block-type pilot, which is a common pilot pattern in SC-FDMA communications and is used in other wireless communication standards. Simulation results show that the suppression performance keeps smooth while phase noise and CFO varies, and BER performance degradation can be significantly reduced in 3 dB.

Based on the substrate integrated waveguide (SIW) technology, the influence of SIW cavity on phase noise of W‐band oscillator is studied and a novel W‐band low phase noise GaAs Gunn planar harmonic oscillator is developed in this letter. The technique of harmonic extraction from Gunn diodes and the novel SIW cavity structure with short piston, which is introduced to study the influence of SIW cavity on phase noise of oscillator, are discussed in detail. Because of the high quality factor and planar structure of the SIW cavity resonator, the oscillator is characterized by some advantages such as low phase noise, small size, low cost and planar integration. The optimal phase noise is −105.81 dBc/Hz at 1 MHz offset 92.16 GHz carrier frequency and the measured output power is more than 6.2 dBm. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1239–1242, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26002

The optical source phase noise is one of the main factors influencing the noise performance of fiber-optic interferometric measurement systems. The phase noise is directly proportional to the optical path length difference of the interferometer and wavelength instability of the optical source. Conventional phase noise suppression techniques involve the use of highly stable optical sources and reduction of path length differences of sensing interferometers. However, such methods are not always appropriate for all interferometric configurations. Alternative phase noise suppression techniques suggest the use of an auxiliary reference interferometer for independent measurements of the phase noise. In this case, the phase noise signal can be directly subtracted from the sensor signal. But equal path length differences are required for all interferometers in the measurement system. In this paper, an adaptive phase noise cancellation technique for fiber-optic interferometric sensors is presented. The proposed technique is based on the real-time evaluation of optical path length differences for all interferometers in the measurement system. This approach doesn't require identical path length differences and takes into account their variations caused by environmental conditions. Thus, the optical source phase noise can be independently measured by the reference interferometer and subtracted from the sensor signal with the required attenuation. The results of experimental investigations of the proposed technique for two types of interferometric schemes are presented. It is shown that the proposed technique demonstrates the phase noise reduction up to 30 dB in the frequency range up to 500 Hz.

A 47 GHz LC cross-coupled voltage controlled oscillator (VCO) employing the high-Q island-gate varactor (IGV) based on a 0.13 ?m RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With VDD of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of -95.4 dBc/Hz and -91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-Q IGV. The VCO with IGV exhibited an output power of around -15 dBm, leading to a FoM of -182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).

This work presents a self-biased 5 GHz hybrid class-B/F−1 oscillator for low phase noise and robust startup. The design exploits the concurrent conduction of nMOS and pMOS, when placed on differential sides, to form a differential-mode (DM) high-quality-factor second-harmonic resonator for low phase noise. The same resonator is shared between the main core (class-F−1) and the startup core (class-B), to allow phase noise reduction. The hybrid CMOS oscillator is fabricated in 22 nm fully depleted silicon-on-insulator (FDSOI) using thin-oxide-only devices, operated from 0.5 V supply, and achieves a phase noise <−147 dBc/Hz at 10 MHz offset across 11% tuning range. The peak figure of merit (FoM) is 190 dBc/Hz, and the supply frequency pushing ranges from 20–44 MHz/V, whereas the power consumption is from 15 to 18 mW. To the authors’ knowledge, the hybrid class-B/F−1 oscillator delivers the lowest phase noise using a 0.5 V supply at 5 GHz.