Integrating Compact Thermal Models in CFD Simulations of Electronic Packages

The paper presents a compact thermal model of an electronic component enclosed in a D2Pak case.The model includes convection cooling and is compared to a linear model with isothermal boundary condition.The model presented is a static model.

A study on the heat dissipation of high power multi-chip COB LEDs

Compact thermal models (CTMs) are used to evaluate thermal characteristics of critical electronic chip packages under several hypothetical design and usage scenarios. In order to ensure that CTMs accurately estimate thermal response, an appropriate set of model parameters must first be selected. The challenge arising in this paper is to glean a set of parameters that best describes the performance of CTM over a set of test conditions. We examine a non-convex optimisation formulation for this parameter estimation problem, and derive the first exact optimisation algorithm for the problem using a continuous version of the reformulation-linearisation technique. We provide experimental results on real data to demonstrate the applicability of our approach.

A methodology is presented for development of compact thermal models for a family of electronic packages, ceramic pin grid arrays (CPGA), in a form compatible with computational fluid dynamics (CFD) codes. A compact model of a CPGA was created and its performance investigated in numerical wind tunnel tests. The results were compared with a detailed CFD model of the package previously validated with experimental results available in the literature. The CFD compact model was able to predict the junction temperatures within 5% of those calculated by the detailed model for flow velocities ranging from 0 to 5 m/s (0 to 1000 ft/min) and three different heat sink configurations. The effects of coarsening the grid were also investigated and the results show that the compact model predicts the junction temperature accurately, whereas the detailed model increasingly loses accuracy as the grid is coarsened.

In order to predict and manage the thermal behavior of microelectronic packages cooled principally by natural convection, a two-way coupling method was developed between a accurate conduction model and a computational fluid dynamics (CFD) simulation. An iterative solution loop was performed by applying as a boundary condition the local convection coefficients obtained from the CFD to the conduction model, and the temperature field at the solid-fluid interface obtained from the solid conduction model to CFD simulation. For the first iteration, the conduction heat transfer was solved by considering an initial guess of a uniform convection coefficient (e.g. from empirical formulas) for each solid-fluid interface. The procedure was repeated until the convergence of the solution was reached. The comparison between the total convection coefficients including the radiation obtained with the CFD iterative procedure and those from the conventional empirical methods showed important differences, thus demonstrating the usefulness of the CFD approach to obtain accurate thermal results. The numerical results were compared to measurements from a test vehicle, carried out under the natural convection Jedec JESD51 standards in a still air chamber. Radiation plays an important role in heat transfer in this setting because of the large temperature difference between the walls of the box and the test vehicle. The junction temperatures obtained with the numerical simulation for different operating powers were in good agreement with the experimental measurements, with an error of less than 1°C, showing that the proposed methodology allows the accurate simulation of the natural heat transfer for microelectronic packages mounted on PCB in the horizontal orientation.

With SiC, junction temperatures of power semiconductors of more than 700?C are theoretically possible due to the low intrinsic charge carrier concentration of SiC. Hence, a lot of research on package configurations for power semiconductor operation above 175?C is currently carried out, especially within the automotive industry due to the possible high ambient temperatures occurring in hybrid electric vehicles (HEVs). This paper shows, that a higher junction temperature though does not necessarily guarantee a higher utilization of the SiC chips with respect to the current that the device can conduct without overheating. The reason is, that for most power devices the power losses start to increase very rapidly at high junction temperatures while the power that can be dissipated always increases linearly with the junction temperature. The junction temperature, where the device current starts to decrease at, is derived for different SiC chips using measured onstate conduction and switching losses in this paper. This paper furthermore analyzes in detail, how the junction temperature on the one hand is influenced by boundary conditions and on the other hand influences itself the core parameters of a converter such as efficiency, the required chip area (i. e. cost) as well as the volumetric power density and thus forms an additional degree of freedom in the design of a power electronic converter. While calculating the optimum junction temperature and analyzing its impact on the system performance, it is demonstrated, how these results can help to find the best suited power semiconductor device for the particular application. The performance of the calculations is shown on a design applied to a drive inverter for hybrid electric vehicles with normally-off SiC JFETs. Operated close to the optimum junction temperature of the SiC JFETs, it reaches a power density of 51 kW/l for the power modules and the air-cooling system, which is shown to be doubled by increasing chip size and using an advanced power semiconductor package with a lower thermal resistance from junction to ambient than the for this case assumed 1 K/W.

The goal of this research is to develop a Dynamic Compact Thermal Model (DCTM) of electronic packages. The general objectives of thermal modeling are to increase the accuracy of electrical analysis by taking the effect of temperature variation into consideration, predicting the reliability of the product, and acquiring the information which is necessary to design the cooling system in order to enhance the performance of the electronic systems. The project is focused on generating the dynamic compact thermal model of electronic packages so that the transient thermal behaviors of the package could be predicted fast and accurately. The approach proposed by DELPHI consortium (a collaborative European project) for static compact thermal model generation is extended in this work to generate the dynamic compact model of a BGA package represented by a RC network or admittance matrix. Two steps performed as the methodology of dynamic compact model generation in this work are: 1- A static compact thermal model of BGA package is generated and validated from the static thermal simulation and 2- A RC network is proposed as the contribution of this work and calculated by optimization as the dynamic compact thermal model of the package using the data of transient simualtion. The size of the proposed RC network then is optimized by eliminating some capacitors from the original RC network and validated by comparing its output to the ouptut of finite element simulation. COMSOL©, a Finite element analysis tool is used for thermal simulation and detailed steady state and transient model generation. The optimization algorithm implemented for both static and dynamic compact model generation is Nelder-Mead multidimensional optimization which is realized by MATLAB© programming. The obtained results from the compact models for both static and dynamic analysis of the BGA package are in agreement with the detailed thermal model results and with the available results in literature.

Thermal management is critical in development of hybrid and electric vehicles since they contain multiple high-density power modules that require compact integration and effective cooling. During operation the power modules generate large amounts of heat leading to significant temperature increases and thermal gradients inside dies and across the packages. Electro-thermal simulation is needed to choose the best operating regime to meet the thermal and electrical requirements. However, this is usually computationally expensive. One effective method is to develop a compact but accurate thermal model to capture the thermal physics that can be used in the system-level electro-thermal model. In this paper an effective Model Order Reduction (MOR) is developed that drastically reduces the number of Degree of Freedoms (DOFs) of the original large-dimension ODE system. Finite Element Analysis (FEA)/ Computational Fluid Dynamics (CFD) simulation is first conducted to find the optimal pin-fin to rear channel ratio and the optimal pin fin shape that gives lowest peak temperature and pressure drop. The convective heat transfer coefficients exacted from FEA/CFD is input to the MOR model. The MOR model is then applied to a converter assembly, and results show that it can reduce the computation time from 2 hours to 1 second with reasonable error compared to the FEA/CFD predictions. The MOR thermal model can be further coupled with electrical circuit models to form a system model to predict the temperature profile and the power modules’ electrical transient performance.

In this paper it is shown how parametric dynamic compact thermal models can be exploited for the calibration of detailed thermal models of electronic components and packages. A constrained least square fit of the thermal response of a parametric dynamic compact thermal model, having as parameters the material thermal properties and geometrical details to be calibrated, onto the measured temperature response is performed. Numerical results show that the use of parametric dynamic compact thermal models instead of detailed compact thermal models, in conjunction with an optimization algorithm solving the constrained least square problem, can reduce the computational time for calibration by more than two orders of magnitude.

Computational Fluid Dynamics (CFD) deals with computing the equations of fluid flows using numerical methods instead of partial differential equations. The Discrete-Event System specification (DEVS) theory has already been used to approximate various continuous systems by applying a quantized state system approach. In this research, we experiment with a new method: using Cell-DEVS theory to create a uniform set of rules for CFD to apply to each cell and execute the state changes of the cells asynchronously. This harmonized set of state changes can effectively render the fluid dynamics, by applying the accurate rules that represents the behavior of the fluid.

A case study investigation into the effects of spatially dependent convection coefficients on the fatigue response of a power plant header component

Efficient thermal management is essential for the reliability and performance of traction inverters. However, direct optimization via Computational Fluid Dynamics (CFD) is often impractical due to the high dimensionality of the design space and the high computational cost of each simulation. To overcome this limitation, a surrogate-based optimization framework is developed to enhance the thermal and hydraulic performance of an automotive traction inverter cooling system. The methodology integrates CFD, deep neural networks (DNNs), and a multi-objective evolutionary algorithm. A simplified representation of the ACEPACK TM DRIVE power module is employed to generate an extensive dataset through automated, GPU-accelerated CFD simulations, making data generation computationally feasible while avoiding the prohibitive cost of direct optimization. A DNN surrogate model is trained to accurately predict pressure drop and heated-wall temperature, achieving mean relative errors below 3% and 1%, respectively. This surrogate model then guides a Non-Dominated Sorting Genetic Algorithm III in the optimization of key geometric parameters, including pin-fin diameter, spacing, height, wall clearance, as well as of physical parameter such as the surface roughness of the pin-fins. CFD-based validation of the Pareto-optimal designs, performed on the full inverter geometry, indicates reductions of up to 25% in pressure drop and approximately 2% in junction temperature. These results suggest that the proposed methodology promises robustness and generalizability, showing good potential for further application in data-driven thermal design optimization.

As a vital part of renewable energy and electrical traction, power converters are supposed to have high reliability and good performance. However, power semiconductors produce considerable heat when the power converter works, which results in high junction temperatures that lower the reliability and performance of the power semiconductors. Many studies show that ambient humidity has a significant effect on power devices, but the influence of high humidity on junction temperatures has yet to be studied. Therefore, this paper presents a thermal model for power converters in moist air to obtain the junction temperature increase, which is utilized for the power converter used in a Switched Reluctance Motor System. Simulation results show that the law of converter temperature distribution is independent of the relative humidity in the case of fixed ambient temperature, whereas the temperature in the power converter decreases as the ambient relative humidity increases. These simulation results are validated with the experimental results.

Modular Multilevel Converter (MMC) is widely used in flexible HVDC transmission systems, IGBT module as its core power device, its failure process seriously affects the operation reliability of MMC. The high junction temperature is an important reason for the failure of the IGBT module, so monitoring the junction temperature of IGBT module is an important means to ensure the stable operation of the system. According to the topological structure of IGBT module, the current junction temperature monitoring methods of IGBT module are summarized and compared. According to the shortcomings of the current research and the current research status, the research direction of IGBT module junction temperature monitoring is prospected.

In order to improve the reverse voltage capacity and low junction temperature characteristics of the traditional silicon-based Schottky diode, a Schottky diode with high reverse voltage capacity and high junction temperature was fabricated using ion implantation, NiPt60 sputtering, silicide-forming and other major technologies on an N-type silicon epitaxial layer of 10.6–11.4 μm and (2.2–2.4) × 1015 cm−3 doping concentration. The measurement results show that the junction temperature of the Schottky diode fabricated can reach 175 °C, that is 50 °C higher than that of the traditional one; the reverse voltage capacity VR can reach 112 V, that is 80 V higher than that of the traditional one; the leakage current is only 2 μA and the forward conduction voltage drop is VF = 0.71 V at forward current IF = 3 A.