Interference-aware frequency-agile onboard processor using fine-grained multilevel analysis-synthesis filter-bank channelization.

This work presents a proficient approach of designing an M-band Near Perfect Reconstruction (NPR) Cosine Modulated Filter Bank (CMFB) where the NPR condition is built upon to satisfy the power complementary property and the pass-edge frequency is repetitively varied to adjust the filter-coefficients to reduce the reconstruction error occurred. Using this optimal value of the pass-edge frequency, the prototype filter is designed and the filter bank is considered from that single prototype filter. Thus the primary goal of designing the CMFB comes down to the issue of implementing efficient structure of this prototype filter. Now the prototype filter is designed with Interpolated Finite Impulse Response (IFIR) technique where numbers of hardware multipliers are reduced by cascading model and image suppression filter compared to that of single prototype filter and furthermore the designed filter coefficients are replaced with Canonical Signed Digit (CSD) to get lesser hardware complexity. To make the system practically realizable, an Electrocardiogram (ECG) signal is processed through this system and reconstructed back again. Some quality measurement parameters such as Signal-to-Noise Ratio (SNR), Mean Square Error (MSE) and Percentage Root Mean Square Difference (PRD) are analyzed to see the effectiveness of the CMFB.

Filter bank multicarrier modulation is one of the most researched techniques in recent wireless communications literature. It is robust against channel frequency selectivity, but it does not require cyclic prefix to compensate for intersymbol interference. Therefore, filter bank multicarrier modulation is superior to orthogonal frequency division multiplexing in terms of spectral efficiency. However, this comes at the cost of higher implementation complexity. Despite the vast published research on filter bank multicarrier modulation, little attention has been given to providing a detailed implementation supported by sufficient mathematical analysis. This is particularly true about the prototype filter section, which is the main source of implementation complexity. In this paper we try to fill this gap by presenting a detailed implementation based on the use of simple sub-channel prototype filters. Sub-channel prototype filters are shorter than a single prototype filter by a factor that is equal to the number of data symbols per multicarrier symbol, resulting in reduced complexity and added design flexibility. Detailed mathematical analysis is provided to support the validity of the proposed implementation.

A proficient approach to the design of Quadrature Mirror Filter (QMF) Bank is studied and an algorithm is offered for straightforward accomplishment of QMF bank with near perfect reconstruction. Objective function is built upon perfect reconstruction condition. The cutoff frequency is repetitively varied to adjust the filter coefficients using the anticipated algorithm and reconstruction error is minimized. Using the optimal value of cutoff frequency the prototype filter is designed and other filters of the bank is considered from that single prototype filter. Kaiser and Dolph-Chebyshev window functions are used to investigate the betterment of the design method. The performance of the projected design method are evaluated in terms of computation time required i.e. CPU time, Perfect Reconstruction Error (PRE), Magnitude Square Error (MSE) and Number of Iterations (NOI). The proposed algorithm is simple, easy to implement, and linearly converges to optimal solution. Finally, the sub-band decomposition of an audio signal is done using the filter bank.

A very simple heterodyne tunable filter can be designed with up-samplers, two heterodyne units, two low pass filters, a single prototype filter and a down-sampler. A complicated prototype band pass filter can be tuned over a range of 90-degrees in the unit circle by simply changing the heterodyne frequency. The simple heterodyne tunable filter offers hardware savings over the other heterodyne filters at the cost of a smaller tuning range and the need for the fixed low-pass filters to remove images.

Repeaters equipped with on-board digital baseband processing in a time division duplex (TDD) demand short processing time in order to alleviate inter-symbol interference resulting from having a time delay that is greater than the guard time. To accomplish this, the total system delay of the repeater should be minimized as much as possible without distorting signal quality. Conventionally, the finite impulse response (FIR) type of filter is deployed as a channelization filter, but due to the necessity of large numbers of coefficients to fulfill a prerequisite filter response with a sharp transition band characteristic, an unwanted excessive time delay intrinsically occurs. To make the processing delay as low as possible, this paper proposes a method employing a minimum-phase characterized infinite impulse response (IIR) filter whose magnitude response is almost identical to that of the original FIR filter. Furthermore, in order to linearize the phase response of the designed IIR filter, this paper also introduces an all-pass filter cascaded with the IIR filter for digital down-conversion as well as up-conversion. To achieve further simplicity, this paper introduces polyphase-style IIR filters transformed from conventional single IIR filters that have their own all-pass filters in order to linearize the phase response. The computer simulation results verify that the proposed integrated IIR filter exhibits a relatively short processing delay with a minor deterioration in signal quality-like error vector magnitude (EVM) performance.

This article presents an analytic development for the design of linear-phase FIR digital filters with reduced computational and hardware complexity. The proposed approach is based on a frequency transformation implemented by replacing a subfilter in a prototype filter. The previous approach forced subfilters and prototype filters to be of odd length, while this approach supports subfilters and prototype filters of even length. Depending on the specifications of the filter, either the previous method or our proposed method can give the optimal solution for the design of the required filter. It has been shown by means of an example that the overall composite FIR filter with the proposed approach contributes to a saving of 22%, 22% and 22% in the number of adders, delays and multipliers respectively compared to the previous approach.

Wave digital filters (WDF's) are well known to have a low‐sensitivity property in general. In addition to several existing design approaches, new circuit realizations of series and parallel sections are proposed in this paper. Also, equivalent transformations are presented which enable new WDF's to be derived from those of Fettweis. Accordingly, many kinds of equivalent WDF's can be designed from a single analog prototype filter. The comparison of sensitivity characteristics of these circuits shows that far less sensitive WDF's can be realized by an appropriate choice from the conventional and the new sections depending on the value of their internal multiplier coefficients.

Digital filterbanks in hearing aids employ an array of filters to selectively amplify sound of different frequencies to compensate hearing loss. The use of filterbanks leads to a higher usage of silicon area as there are many filters, each generating a sub-band. Reconfigurable warped digital filter is a Variable Digital Filter (VDF) that can be reconfigured to function as a low-pass, band-pass or high-pass filter with cutoff frequencies that can be varied on-the-go. We propose a system with reconfigurable warped VDF that uses a single prototype filter for generating all the necessary sub-bands. The proposed system automates the generation of the control signals for reconfiguring the filter and pipelines the processing of each sub-band to generate the requisite magnitude response. The proposed architecture is designed to achieve good audiogram matching with minimum matching error.

A polarization maintaining single mode fiber birefringent filter which could function as a two channel, three port wavelength selective multiplexer/demultiplexer has been designed, constructed, characterized, and evaluated. A highly accurate and novel procedure was used to measure the wavelength dependence of the beat length of the AT&T rectangular PM fiber used in the prototype filter. In addition, a computer simulation of birefringent filters (based on a new first principle theory of polarized signals in birefringent media) was used as a design tool and found to be in excellent agreement with the spectral response of the prototype filter. The free spectral range of the prototype filter is 326 nm with pass/stop bands of 36 nm and 45 nm about the 1373.2 nm and 1533.3 nm wavelengths, respectively. The insertion loss, which was not optimized, was 4.3 dB. The crosstalk was -11.3 dB and -24.2 dB for the parallel and crossed orientations of the polarizers.

In this paper, a constrained optimisation technique is used to design quadrature mirror filter banks with linear phase in frequency domain. A unique method is developed in which the design problem is formulated as a constrained optimisation that minimises the weighted sum of error of transfer function of the filter bank at quadrature frequency, stopband energy, the passband error and measure of ripple of the prototype filter. Numerical examples and comparisons with several existing methods are included to show the performances and the effectiveness of the proposed method in terms of reconstruction error, mean square error in passband and mean square error in stopbands.

This paper presents an area-efficient 4- stream finite impulse response (FIR) interpolation/decimation for IEEE 802.11n wireless local area network (WLAN). Novelty of the presented design is threefold. First, a multi-path pipelined polyphase structure is proposed to deal with multiple data streams, thereby four simultaneous data streams can be supported in the design with minimal hardware complexity. Second, a hybrid common subexpression elimination (HCSE) method that using signed binary representation of coefficients is applied to the implementation of subfilters. The multiplications in each subfilter are efficiently implemented using a few hardwired shifts, adders, and subtracters. And last, the interpolating mode and decimating mode of the design are configurable. That help to improve system level hardware utilization efficiency since WLAN is a time division duplex system. Under 0.13 μm 1.2 V 1P6M CMOS technology, the cell area and power consumption of the presented interpolation/decimation are 0.22 mm2 and 10.08 mW respectively. The error vector magnitude (EVM) performance of an 802.11n baseband prototype which adopts the presented design is measured ?42.2 dB.

A low-power, pulse-operation-based nonlinear distortion statistics module is proposed, comprising a nonlinear distortion error conversion unit and a nonlinear distortion error extraction unit. This module enables high-accuracy characterization of Ka-band power amplifier (PA) nonlinearity, providing critical guidance for advanced self-adaptive linearization. A novel nonlinear distortion statistical characteristics theory is introduced, leveraging the cumulative probability distribution (CPD) of PA input and output envelope voltages. Based on this theory, a search method for maximizing the accuracy of nonlinearity characterization is developed, mainly focusing on the dynamic range. The proposed statistics module is implemented in a 65-nm CMOS process. The nonlinear distortion error conversion unit first characterizes nonlinear distortion through a dual-path peak detector and comparators. Subsequently, the nonlinear distortion error extraction unit extracts the nonlinear distortion error signal using only logic gates and an error integrator, which performs an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xor</small> operation followed by a summation operation to derive the error. This design significantly reduces hardware complexity while maintaining high accuracy. Prototype verification is conducted through two scenarios. Characterizing accuracy, mainly focusing on the dynamic range, is validated by cascading the statistics module with an analog linearizer. A CMOS PA integrated with an analog linearizer is utilized as an example to demonstrate the potential for self-adaptive PA linearization. The characterizing accuracy measurement results demonstrate that the proposed module achieves a normalized dynamic range better than 0.57. In the self-adaptive PA linearization measurement, the statistic module’s iterative guidance for linearization achieves the adjacent channel power ratio (ACPR) of −35 dBc and an improvement of 2.2% in error vector magnitude (EVM). With a low power consumption of only 30 mW, the proposed statistics module achieves high accuracy in nonlinear characterization and provides a self-adaptive linearization solution for millimeter wave (mmWave) PAs, demonstrating the significant potential for advanced self-adaptive linearization applications.

A new control scheme for a single phase shunt Active Power Filter (APF) is proposed in this paper. The goal is the introduction of a new reference generator along with a repetitive current control scheme. The proposed reference generator uses a filter based on a sinusoidal signal integrator and the instantaneous reactive power theory to compute the APF reference current. The proposed scheme can be easily adapted to work in a distributed generation system, injecting active power into the grid. The whole control algorithm has been implemented on the dSPACE DS1103 development system controlling a single phase APF prototype to demonstrate the feasibility of the proposed solution.

Spectrum sensing is an efficient way to determine the spectrum availabilities over the frequency range of interest, aiding in improving the spectrum utilization in the cognitive radio (CR) systems. Conventional Nyquist multiband sensing entails higher computational capability for sampling, quantization, and subsequent processing, lending the approach infeasible for applications with limited power budgets. In this brief, a power-efficient spectrum-sensing technique is proposed, which explores an accuracy-complexity tradeoff. The presented spectrum-sensing architecture is based on 1-bit quantization at the CR receiver and implements it in hardware by a resource- and power-efficient approach, using a finite-impulse-response (FIR) filter-bank channelizer. The proposed scheme allows the complex operators like multipliers and quantizers to be replaced by the inverter logic and high-speed comparators, reducing the hardware complexity and power consumption. We validate the proposed scheme on a field-programmable gate-array (FPGA) emulator for an aeronautical L-band digital aeronautical communication system (LDACS) application, and our results show that the proposed scheme achieves substantial resource reduction with at most 5% degradation in the detection accuracy in this case.

In this paper, we consider optimizing the prototype filter of biorthogonal cosine-modulated filter banks in order to reduce overflow occurrence in a fixed-point implementation. We assume that the wordlength of the fixed-point implementation is constant throughout the implementation. We implement the polyphase filters in a form which is inherent to perfect reconstruction. However, the frequency response is subject to fixed-point error, most dominantly overflow. We demonstrate that the floating-point prototype filter with the lowest stopband energy does not result in the fixed-point implementation with the best performance. Based on this result, we show how the fixed-point performance can be improved by preventing amplification by large filter coefficients and by modifying the cost function of the optimization in such a way that all filters have a similar gain. Since the filter bank allows an integer-to-integer mapping with no increase in wordlength, it is well suited for lossless compression algorithms as well as a fast and inexpensive implementation on a hardware platform with fixed-point number format.