Introduction to Cryptography and Advanced Encryption Standard

The Consultative Committee for Space Data Systems (CCSDS) recommends AES algorithm as a cryptographic algorithm to maintain confidentiality and data security between spacecraft and ground systems. In implementation, there are several AES algorithm operating modes including Cipher-Block Chaining (CBC), Electronic Codebook (EBC), Cipher Feedback (CFB), Output Feedback (OFB), and counter mode (CTR). One of the operating modes of AES algorithm recommended by CCSDS is CTR because it has advantages in terms of efficiency of implementation and offers a high level of data security. LAPAN-A4 as the next generation of LAPAN satellites also uses CCSDS standard in terms of data exchange between satellites and ground stations including telemetry and telecommand (TTC) data and satellite payload data. In order to protect LAPAN-A4 satellite data, especially TTC data, in this paper AES algorithm was implemented in CTR operating mode on the FPGA which will then be implemented on LAPAN-A4 satellite onboard data handling (OBDH) as one of LAPAN-A4 satellite data security systems. To overcome the limited resource of FPGA, optimization is also done using basic iterative AES hardware reused method, which is to reuse hardware that has been designed n times for same operation for AES algorithm. From the results of implementation and optimization, efficiency of logic gates used is increasing almost a quarter less than the previous research.

Hardware Trojans pose a significant threat to the security and integrity of cryptographic systems, particularly in Advanced Encryption Standard (AES) implementations, which are widely used in securing sensitive data. These malicious modifications to integrated circuits (ICs) can compromise the confidentiality and reliability of AES cryptographic operations by introducing covert backdoors, information leakage channels, or functional disruptions. Hardware Trojans are typically designed to evade detection during design-time validation and post-manufacturing testing, often activating only under specific triggers such as rare input patterns or environmental conditions. In AES systems, Trojans can manipulate the encryption process by leaking secret keys through side-channel information such as power consumption, timing variations, or electromagnetic emissions. Some Trojans directly alter the encryption algorithm, weakening the cryptographic strength and rendering encrypted data vulnerable to attacks. Attackers may also embed Trojans at the Register Transfer Level (RTL) or gate-level design, leveraging the inherent complexity of AES circuits to conceal their presence. Detection and mitigation of hardware Trojans in AES implementations are challenging due to their stealthy nature. Techniques such as side-channel analysis, functional verification, and static code analysis have been developed, but sophisticated Trojans often bypass these methods. Advanced countermeasures include runtime monitoring, hardware obfuscation, and Trojan-resilient design methodologies. This paper explores the implications of hardware Trojans in AES cryptographic systems, analysing their design, potential attack vectors, and impacts on data security. Furthermore, it discusses state-of-the-art detection and prevention techniques, highlighting gaps and future research directions. Given the critical role of AES in securing financial, military, and consumer data, addressing the hardware Trojan threat is paramount to ensuring trust in cryptographic hardware and safeguarding against adversarial exploitation.

Data security and encryption is one of the most useful at highly essential aspects of enabling effective security of the data against attacks and intrusions. This is an effective and useful technique that has been evolved significantly over the past few years. For the purpose of encryption the AES was prominently used before. The data encryption standard is highly effective but was prone to encryption failure against brute force attacks that have been highly effective against this encryption standard. Therefore the advanced encryption standard has been used since then to improve the performance of encryption significantly. The advanced encryption standard has been useful and realization of effective security but has been optimized specifically for achieving high throughput and high bandwidth for a variety of implementations. In this methodology we propose an enhancement to the AES encryption approach through the improvement of key generation process through the utilization of the genetic algorithm. The effective and useful implementation of genetic algorithm has been significantly useful for improving the performance of the AES encryption con siderably. Keywords: Data Security, Advanced Encryption Standard (AES), Genetic Algorithm, Key Generation, Cryptography

This study discusses the effectiveness of using AES (Advanced Encryption Standard) and RC4 (Rivest Chipper 4) as digital data security algorithms to prevent and protect transaction data from irresponsible parties. This needs to be done because the development of sales transactions or other services has used digital technology a lot. This situation causes the need to secure digital data from existing transactions, so that transaction data can be stored safely. Transaction data security is carried out by changing data into ciphers or codes that are difficult to read using the AES (Advanced Encryption Standard) and RC4 (Rivest Cipher 4) algorithms. This research begins by collecting existing transaction data and then transforming it into ASCII code. The results of the transformation will be used to perform calculations using the AES algorithm. After completing the calculation process using the AES algorithm, then do the calculations using RC4. These results will be stored in the database so that the transaction data that has turned into these codes cannot be known by other parties. The combination of the AES and RC4 algorithms is carried out to strengthen data encryption because there are more and more rotation systems and double security is carried out so that digital data is not easily read and misused. With the presence of this research, it can be shown that the AES and RC4 algorithms are capable of encrypting existing transaction data with multiple levels of security.

Data security is the focus of information security. As a primary method, file encryption is adopted for ensuring data security. Encryption algorithms created to meet the Data Encryption Standard (DES) and the Advanced Encryption Standard (AES) are widely used in a variety of systems. These algorithms are computationally highly complex, thus, the efficiency of encrypting or decrypting large files can be drastically reduced. To this end, we propose an optimized algorithm that efficiently encrypts and decrypts large files by parallelizing processing tasks on a single heterogeneous many-core processor in the Sunway TaihuLight computer system. Firstly, we convert the serial DES and AES programs to our experimental platform. Then we implement a task assignment strategy to test the converted algorithms. Finally, in order to optimize parallelized algorithms and improve data transmission performance, we apply the master-slave communication optimization, the three-stage parallel pipeline, and vectorization. Extensive experiments demonstrate that our optimized algorithm is faster than the state-of-the-art open-source implementations of DES and AES. Compared with the serial processing algorithms, our parallelized DES and AES perform nearly 40 times and 72 times faster, respectively. The work described in this paper leverages existing methods and provides a sound basis for the direction of future research in data encryption.

Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

The National Institute of Standards and Technology (NIST) of US announced Rijndael algorithm as the advanced encryption standard (AES) in October 2000, Despite AES surpassing in security the data encryption standard (DES), it is still rare to be implemented in smart cards, due to the reason of deficient AES coprocessors. Here a chip operation system (COS) called NexCard, which derived from Microsoft's Windows COS, is used as the AES implementation platform. After a suitable COS architecture design for AES and methodology of efficient memory usage, the simulation result shows that direct embedding AES encryption attains 0.56 ms at system clock 15 MHz on the INFINEON SLE66CX322P chip without existence of coprocessor. Corresponding to the development needs in smart card cryptographic algorithm implementations, and different level of the security design specifications, a concept to conjoin numbers of algorithms into single smart card called cipher system on demand (CSOD) method is accomplished in this study concurrently. This is a method utilizing the multiapplication capability of NexCard v2.0 to execute the same AES algorithm as an on-card applet. Although the performance of CSOD is not as good as AES embedded method, CSOD can provide the same result in the situation of adaptability and extendibility.

Cloud security is an evolving sub-domain of computer and network security. Cloud platform utilizes third-party data centers model. An example of cloud platform as a service (PaaS) is Heroku. It supports several programming languages that are used for web application deployment model. Heroku is based on a managed container system, with integrated data services and a powerful ecosystem, for deploying and running modern apps. One essential issue in cloud computing is data security, which is handled using cryptography methods. A possible method to encrypt data is Advanced Encryption Standard (AES). In this paper, we implement Heroku as a cloud platform, then we implement AES for data security in Heroku. The performance evaluation shows that AES cryptography can be used for data security. Moreover, delay calculation of data encryption shows that larger size of data increases the data delay time for encrypting data.

File-sharing activities become a bridge for communication in the form of data between one party and another party. File sharing allows users to share data with other users, by uploading data to the server computer and other users can download data from the server computer. A document security system is indispensable to keep document data safe until its destination. File Web Sharing will transmit data with cryptographic methodologies. The algorithm used is Advanced Encryption Standard (AES), Data Encryption Standard (DES), and Blowfish. This study aims to compare the performance of AES, DES, and Blowfish algorithms when implemented to secure file sharing. Performance research results show that the DES algorithm is on average 8.35% faster than AES and the Blowfish algorithm is 7.11% faster than AES. Memory usage capacity testing shows that the AES algorithm requires 4.82% greater memory capacity than Blowfish, and the DES requires 2.41% greater memory capacity than the Blowfish algorithm. Kegiatan file sharing menjadi jembatan komunikasi data antara satu pihak dengan pihak lainnya. File sharing memberikan pengguna kemampuan untuk berbagi data dengan pengguna lain, dengan cara mengunggah data ke komputer server dan pengguna lain dapat mengunduh data dari komputer server. Sistem keamanan terhadap dokumen sangat diperlukan untuk menjaga data dokumen tetap aman sampai tujuannya. Web File Sharing akan mengirimkan data dengan metodologi kriptografi. Algoritma yang digunakan adalah Advanced Encryption Standard (AES), Data Encryption Standard (DES), dan Blowfish. Penelitian ini bertujuan untuk membandingkan kinerja algoritma AES, DES dan Blowfish saat diimplementasikan untuk mengamankan file sharing. Hasil pengujian kinerja menunjukkan bahwa algoritma DES rata-rata 8,35% lebih cepat dibandingkan AES sedangkan Blowfish 7,11% lebih cepat dibandingkan AES. Berdasarkan pengujian kapasitas penggunaan memori terlihat bahwa AES membutuhkan kapasitas memori 4,82% lebih besar dibandingkan Blowfish dan DES membutuhkan kapasitas memori 2,41% lebih besar dari Blowfish.

The meaning of security is to protect something important from not authorized peoples. Cryptography is one of the security systems. Many applications could be used in the security systems like military applications, email, banking, information technology of database. The proposed system uses advanced encryption standard(AES) with secure hash algorithms(SHA-1) to produce a strong ciphertext. Moreover, this paper make the combination of (SHA-1) which is a one way encryption, as a key with (AES) algorithm which is a two way encryption as a ciphering generator to obtain confidentiality and integrity, In this paper presented implementation of Advanced Encryption Standard (AES) and Secure Hash (SHA-1) Algorithm by the use of FPGA Hardware card, However implementation of the AES algorithm and SHA-1 using LABVIEW environment with MATLAB system generator to generate stream data to FPGA hardware target. The output of the hash function is used as an input key for AES in order to improve data security, From the algorithms result of AES and SHA-1 obtained in FPGA, the system obtained how it is simple in modeling hashing and AES algorithms, generating hash codes and plain texts in (small and capital letters), symbols and numbers. The FPGA card used in this system (Spartan 3AN)with frequency (50%), the complete system take (1,147)size from the available space of (11,776) and accuracy (90%),the system work properly.

Nowadays most of the data transmission is done through digital communication and hence security and efficient data transmission is always a desirable property for any data communication. At present, Advance encryption standard (AES) is most widely used cryptographic technique. This AES uses static s box for encryption and decryption which remains constant irrespective of the key. Numerous analysts have experimented and revealed that there are some weak points [1] in the static s-box as it is static and known to all. Therefore, in our proposed algorithm we modify AES such that it uses dynamic sbox which is key dependent and compare the avalanche effect of basic AES with our proposed algorithm.

Four Dimensional (4D) Playfair cipher fused with Linear Feedback Shift Register (LFSR) has the capability of providing confidentiality to any type of data. The main aim of this research is to compare this cipher with the standard ciphers AES-256 and RSA-2048. The comparisons are done on the basis of encryption and decryption times, plain data size versus cipher data size, possible number of keys and types of data supported. It is found from the comparison analysis that the AES-256 is efficient in terms of time, memory and bandwidth consumption when compared to the other two ciphers. For AES-256, data size has to be a multiple of 16 bytes or padded values shouldn’t be a part of original data values in order to be unambiguous while the other two ciphers are always unambiguous. Also, AES-256 is weak against brute force attack when compared to other two ciphers. Among RSA-2048 and 4D Playfair cipher fused with LFSR, latter is highly efficient in terms of time, memory and bandwidth. Therefore, applications wanting to secure all sorts of data efficiently and unambiguously irrespective of data size can use 4D Playfair cipher fused with LFSR. Keywords: Data security; Cryptography; AES; RSA; 4D Playfair cipher

Security has been a primary concern for each type of network to provide secure communication among the users of different types of network. Presently, many techniques are present for providing security in networks but Advanced Encryption Standard (AES) has been proved to be the most prominent, keeping the data security as the major factor in data transmission. In the presented exposition, a modified variant of AES algorithm named as Modified Advanced Encryption Standard (MAES) has been introduced for secure data transmission in wired and various wireless networks namely, MANET, VANET, and FANET. The proposed technique focuses on both prevention and detection of the security attacks on the network. Theoretically, it is difficult to break the security or crack the key in the assumed network. The proposed protocol takes 2256 computations as compared to the basic AES standard which take 232 in case of differential fault analysis. The simulation results show that the proposed MAES outperformed AES in terms of security against attacks such as side channel attacks.

The development of digital world created advancement of technology, by which the data services are electronically transacted. Electronic voting is used to improve the election system in several ways. But technical issues associated with protection of data, is considered as a major concern leading to illegal activities and threats. Some of the conventional methods used in securing e-votes are matching finger prints of individual, control unit accessibility, which provides decreased capability of attaining proper authenticity and security. Even several cryptographic methods are used for data security, but produced limited accuracy. So, to improve the reliability and accuracy of data protection in e-voting, combination of AES (Advanced Encryption System) and RSA (Rivest, Shamir, Adleman) combined with blockchain technology is implemented. AES uses larger key size which makes the data privacy robust. But encryption and decryption time produces decreases computational speed. So, AES is combined with RSA, as it uses shorter key length and easy to implement with block-chain algorithm, it is deployed to decrease encryption and decryption time, thus producing highly sensitive data security. The performance of the system is validated by calculating the encryption and decryption time, block size and verification time of original data with output data.

Encryption and decryption of data with very low latency and high energy efficiency is desirable in almost every application that deals with sensitive data. The advanced encryption standard (AES) is a widely adopted algorithm in symmetric key cryptography with numerous efficient implementations. Nonetheless, in scenarios involving extensive data processing, the primary limitations on performance and efficiency arise from data movement between memory and the processor, rather than data processing itself. In this article, we present a novel in-memory computing (IMC) approach for AES encryption and key-expansion, and experimentally validate it on an IMC prototype chip based on phase-change memory (PCM) technology. We leverage operators stored in PCM crossbar arrays to achieve the flexibility to tune performance at runtime based on the amount of free storage available in the memory system. In addition, we introduce a method for parallel in-memory polynomial modular multiplication and evaluate the potential of intrinsic stochastic properties of PCM devices for random key generation. We show how to further improve efficiency with minimal additional auxiliary circuitry. To evaluate the performance within a custom-built large-scale in-memory AES system, we design and implement a cycle-accurate simulator that integrates parameters from Spice simulations for detailed latency and energy consumption analysis of the AES algorithm. Our evaluations indicate that our IMC-based AES approach outperforms state-of-the-art methods, achieving speed factor improvements of up to 19.7 at equivalent energy efficiency.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.