Investigation of Non-Linear Selection Effect on RRAM based Neuromorphic Computing Array with Passive Selective Element

Memristors are poised to revolutionize neuromorphic computing and next-generation memory, yet persistent challenges, including stochastic conductance control, limited endurance, and poor scalability, impede their practical adoption. Here, we report a self-rectifying memristor leveraging a GaOx/InOx heterostructure to overcome these barriers. The device demonstrates an ultrahigh rectification ratio and nonlinearity (>107), effectively suppressing sneak currents in passive crossbar arrays. Robust multi-level conductance modulation and cycling stability exceeding 106 cycles are achieved, alongside minimal inter-device variability (σ/μ < 10%) in a 6 × 6 passive array. Critically, it demonstrates dynamic tunability between short-term and long-term plasticity, modulated via pulse number/amplitude, a cornerstone for biologically inspired learning. By implementing the one-bitline pull-up scheme, the design achieves an integration density of 125.1 Tb at a 10% read margin, outperforming state-of-the-art resistive memories. This work establishes oxide heterostructures as a scalable platform for high-density neuromorphic systems, bridging the gap between functional material innovation and hardware-driven machine intelligence.

The realization of logic operations within passive crossbar memory arrays is a promising approach to expand the fields of application of such architectures. Material implication was recently suggested as the basic function of memristive crossbar junctions, and single bipolar resistive switches (BRS) as well as complementary resistive switches (CRS) were shown to be capable of realizing this logical functionality. Based on a systematic analysis of the Boolean functions, we demonstrate here that 14 of 16 Boolean functions can be realized with a single BRS or CRS cell in at most three sequential cycles. Since the read-out step is independent of the logic operation steps, the result of the logic operation is directly stored to memory, making logic-in-memory applications feasible.

A bidirectional threshold switching (TS) characteristic was demonstrated in Ag/ZrO2/Pt electrochemical metallization cells by using the electrochemical active Ag electrode and appropriate programming operation strategies The volatile TS was stable and reproducible and the rectify ratio could be tuned to ∼107 by engineering the compliance current. We infer that the volatile behavior is essentially due to the moisture absorption in the electron beam evaporated films, which remarkably improved the anodic oxidation as well as the migration of Ag+ ions. The resultant electromotive force would act as a driving force for the metal filaments dissolution, leading to the spontaneous volatile characteristics. Moreover, conductance quantization behaviors were also achieved owing to formation and annihilation of atomic scale metal filaments in the film matrix. Our results illustrate that the Ag/ZrO2/Pt device with superior TS performances is a promising candidate for selector applications in passive crossbar arrays.

Resistive switching in a metal-free silicon-based material offers a compelling alternative to existing metal oxide-based resistive RAM (ReRAM) devices, both in terms of ease of fabrication and of enhanced device performance. We report a study of resistive switching in devices consisting of non-stoichiometric silicon-rich silicon dioxide thin films. Our devices exhibit multi-level switching and analogue modulation of resistance as well as standard two-level switching. We demonstrate different operational modes that make it possible to dynamically adjust device properties, in particular two highly desirable properties: nonlinearity and self-rectification. This can potentially enable high levels of device integration in passive crossbar arrays without causing the problem of leakage currents in common line semi-selected devices. Aspects of conduction and switching mechanisms are discussed, and scanning tunnelling microscopy (STM) measurements provide a more detailed insight into both the location and the dimensions of the conductive filaments.

Memristor crossbar arrays are expected to achieve highly energy-efficient neuromorphic computing via implementing parallel vector–matrix multiplication (VMM) in situ. The similarities between memristors and neural synapses offer opportunities for realizing hardware-based brain-inspired computing, such as spike neural networks. However, the nonlinear I–V characteristics of the memristors limit the implementation of parallel VMM on passive memristor crossbar arrays. In our work, we propose to utilize differential conductance as a synaptic weight to implement linear VMM operations on a passive memristor array in parallel. We fabricated a TiO2/HfO2 memristor crossbar array, in which differential-conductance-based synaptic weight exhibits plasticity, nonvolatility, multi-states, and tunable ON/OFF ratio. The noise-dependent accuracy performance of VMM operations based on the proposed approach was evaluated, offering an optimization guideline. Furthermore, we demonstrated a spike neural network circuit capable of processing small spiking signals through the differential-conductance-based synapses. The experimental results showcase effective space-coded and time-coded spike pattern recognition. Importantly, our work opens up new possibilities for the development of passive memristor arrays, leading to increased energy and area efficiency in brain-inspired chips.

Electrical properties of Pt interconnects for passive crossbar memory arrays

The high demand for performance and energy efficiency poses significant challenges for computing systems in recent years. The memristor-based crossbar array architecture is enthusiastically regarded as a potential competitor to traditional solutions due to its low power consumption and fast switching speed. Especially by leveraging self-rectifying memristive devices, passive crossbar arrays potentially enable high memory densities. Nonetheless, due to the lack of a switching control per cell, these passive, self-rectifying memristive crossbar arrays (srMCA) suffer from sneak path current issues that limit the range of accurate operation of the crossbar array. In this work, the sneak path current issues in the passive srMCAs based on self-rectifying bipolar and complementary switching memristive devices are comparatively analyzed. Under consideration of the worst-case scenario, three reading schemes are investigated: one wordline pull-up (OneWLPU), all wordline pull-up (AllWLPU), and floating (FL) reading schemes. As a conclusion, despite different switching dynamics, both types of self-rectifying memristive devices can efficiently suppress sneak path current in the srMCAs. In the FL reading scheme, the sneak path current flowing through the unselected reversely biased memristive cells in the srMCA can be considered as an accurate estimation for the practical sneak path current in the srMCA. By analyzing the sneak path current in the srMCAs with a size up to 64 × 64, it is demonstrated that the leakage current plays a crucial role for suppressing the sneak path current, and the sneak path current via an individual cell exhibits a continuous decrease while the accumulated total sneak path current in the unselected reverse biased region is increasing with expanding the crossbar size. The comparative study on the bipolar and complementary memristive devices based srMCAs under diverse reading schemes reveals the influence of the switching dynamics on the sneak path current effect in the srMCAs, and provides a beneficial reference and feasible solutions for the future optimization of the crossbar topology with the intention of mitigating sneak path effects.

Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in‐memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption. Key to analog neuromorphic computing hardware are memristors, providing non‐volatile multistate conductance levels, high switching speed, and energy efficiency. Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation. In this work, a W/Hf x Zr1−x O2/TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m−2 at V read = 0.3 V and highly nonlinear current–voltage (I–V) characteristics (>1100) is experimentally demonstrated. Using a circuit macro‐model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved. Finally, the low on conductance in combination with the highly nonlinear I–V characteristics enable the realization of large selector‐free crossbar arrays for neuromorphic hardware accelerators.

The resistive random access memory (RRAM) has stimulated a variety of promising applications including programmable analog circuit, massive data storage, neuromorphic computing, etc. These new emerging applications have huge demands on high integration density and low power consumption. The cross-point configuration or passive array, which offers the smallest footprint of cell size and feasible capability of multi-layer stacking, has received broad attention from the research community. In such array, correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells. This target requires nonlinear I–V characteristics of the memory cell, which can be realized by either adding separate selector or developing implicit build-in nonlinear cells. The performance of a passive array largely depends on the cell nonlinearity, reliability, on/off ratio, line resistance, thermal coupling, etc. This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration. First, the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures. Next, the state of the arts on the development of various selector devices and self-selective cells are presented. Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles. Then, the reliability issues in 3D array are summarized in terms of uniformity, endurance, retention, and disturbance. Subsequently, scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed, and applications of 3D RRAM beyond storage, such as neuromorphic computing and CMOL circuit are discussed later. Summary and outlooks are given in the final.

Efficiently solving combinatorial optimization problems (COPs) such as Max-Cut is challenging because the resources required increase exponentially with the problem size. This study proposes a hardware-friendly method for solving the Max-Cut problem by implementing a spiking neural network (SNN)-based Boltzmann machine (BM) in neuromorphic hardware systems. To implement the hardware-oriented version of the spiking Boltzmann machine (sBM), the stochastic dynamics of leaky integrate-and-fire (LIF) neurons with random walk noise are analyzed, and an innovative algorithm based on overlapping time windows is proposed. The simulation results demonstrate the effective convergence and high accuracy of the proposed method for large-scale Max-Cut problems. The proposed method is validated through successful hardware implementation on a 6-transistor/2-resistor (6T2R) neuromorphic chip with phase change memory (PCM) synapses. In addition, as an expansion of the algorithm, several annealing techniques and bias split methods are proposed to improve convergence, along with circuit design ideas for efficient evaluation of sampling convergence using cell arrays and spiking systems. Overall, the results of the proposed methods demonstrate the potential of energy-efficient and hardware-implementable approaches using SNNs to solve COPs. To the best of the author's knowledge, this is the first study to solve the Max-Cut problem using an SNN neuromorphic hardware chip.

This chapter introduces resistive random-access memory (RRAM), a futuristic memory technology that excels its counterparts in terms of reliability, nano-scale dimensions, energy per bit, and fast read/write times. Also, it is promising for use in neuromorphic computing and digital applications. However, the major challenge encountered during the progress of the technology is the presence of leakage current (sneak path current) while using it in crossbar arrays. Various techniques are employed to mitigate the sneak current problem. However, associating a selector with RRAM is an efficient method. To study the one selector-one RRAM (1S-1R) characteristics, the electrical model of the selector, as well as RRAM, is necessary; therefore, this chapter discusses the electrical modeling of selector device (1S), RRAM devices (1R), integration of selector models with the RRAM model (1S-1R), and formation of 1S-1R crossbar arrays. The selector device used to model this is Pt/Ta2O5/TaOx /TiO2/Pt, and the RRAM model adopted is Pt/Ta2O5/TaOx/Pt. Further, various parameters are analyzed, such as R off /R on ratio, nonlinearity, and off-current are improved in the 1S-1R cell compared to RRAM characteristics. Besides, it is perceived that 98% of the sneak path current is mitigated in the 1S-1R crossbar array compared to the 1R crossbar array.

Memristive devices offer non-volatile storage capabilities, along with in-memory computation capabilities. Large scale passive crossbar arrays can be enabled by avoiding parasitic paths by means of a select device in series with a resistive switching device (1S1R). In this work, we utilize 1S1R Resistive RAM (ReRAM) arrays for realization of logic-in-memory operations, where each device is capable of performing the Boolean Majority operation with an input inverted. In contrast to the prior works, for the first time, we enable memristor-aided n-input OR operation in the same memristive array - some memristors initialized with data act as input and an additional memristor acts as output. By extending the reach of the underlying devices in terms of logic primitives, we boost the optimization of logical depth and device count. This improvement is demonstrated through a representative case study. This paves the way for new and improved memristive crossbar designs, compared to the state-of-the-art Majority only or NOR only memristive approaches.

Among today’s nonvolatile memories, ferroelectric-based capacitors, tunnel junctions and field-effect transistors (FET) are already industrially integrated and/or intensively investigated to improve their performances. Concurrently, because of the tremendous development of artificial intelligence and big-data issues, there is an urgent need to realize high-density crossbar arrays, a prerequisite for the future of memories and emerging computing algorithms. Here, a two-terminal ferroelectric fin diode (FFD) in which a ferroelectric capacitor and a fin-like semiconductor channel are combined to share both top and bottom electrodes is designed. Such a device not only shows both digital and analog memory functionalities but is also robust and universal as it works using two very different ferroelectric materials. When compared to all current nonvolatile memories, it cumulatively demonstrates an endurance up to 1010 cycles, an ON/OFF ratio of ~102, a feature size of 30 nm, an operating energy of ~20 fJ and an operation speed of 100 ns. Beyond these superior performances, the simple two-terminal structure and their self-rectifying ratio of ~ 104 permit to consider them as new electronic building blocks for designing passive crossbar arrays which are crucial for the future in-memory computing.

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes.

The memristor is a resistive switch where its resistive state is programable based on the applied voltage or current. Memristive devices are thus capable of storing and computing information simultaneously, breaking the Von Neumann bottleneck. Since the first nanomemristor made by Hewlett‐Packard in 2008, advances so far have enabled nanostructured, low‐power, high‐durability devices that exhibit superior performance over conventional CMOS devices. Herein, the development of memristors based on different physical mechanisms is reviewed. In particular, device stability, integration density, power consumption, switching speed, retention, and endurance of memristors, that are crucial for neuromorphic computing, are discussed in detail. An overview of various neural networks with a focus on building a memristor‐based spike neural network neuromorphic computing system is then provided. Finally, the existing issues and challenges in implementing such neuromorphic computing systems are analyzed, and an outlook for brain‐like computing is proposed.