Investigation on a novel discontinuous pulse-width modulation algorithm for single-phase voltage source rectifier

Voltage source converters (VSC) and current source converters (CSC) transfer energy from a source to a load in a quantized fashion using semiconductor switches which are turned on and off at fast repetition rates. Space vector modulation (SVM) among other pulsewidth modulation techniques, offer several advantages such as minimizing the number of switchings or improving the utilization of the source voltage. This paper presents three alternatives for implementing SVM in a DSP-controller. The study is performed for a voltage source rectifier (VSR), but as well, it is adequate for a voltage source inverter (VSI). The three alternatives are compared from a theoretical and experimental point of view. The algorithms proposed provide a simple and effective solution for high-performance (VSR). Experimental results are given to verify the implemented algorithms.

Modern power systems face challenges due to the increasing use of renewable energy sources. To overcome these challenges, cascaded H-bridge (CHB) static synchronized compensators (StatComs) have emerged as promising solutions. CHB StatComs offer the advantage of directly regulating grid voltage and power factor at medium and high voltage levels without the need for additional low-frequency transformers. However, in order to attain the desired medium and high voltage levels, a large number of H-bridge submodules (SMs) are required. Despite each individual SM processing a relatively low voltage, it has to carry the entire leg current. This results in significant switching loss that needs to be carefully considered to ensure thermal reliability and optimal system efficiency in CHB StatComs. Discontinuous pulsewidth modulation (DPWM) is a technique that has gained research attention for its ability to reduce switching loss. In CHB StatComs with a star configuration, DPWM is achieved by injecting a zero-sequence voltage (ZSV) between the neutral of the converter and system ground, which clamps a converter leg ac-side voltage to a fraction of its corresponding cluster voltage (sum of dc-side capacitor voltages per converter leg). The clamped converter leg stops switching, resulting in reduced switching loss. However, unlike two-level converters where a common dc-link is shared by three phases, the single-phase configuration of CHB StatComs, along with the use of floating capacitors in the dc-side of each SM, complicates the use of conventional DPWM methods. This complication is further exacerbated during grid imbalances, as the interaction between grid currents and the ZSV for DPWM can result in nonzero active power transfer to each leg, leading to divergence in cluster voltages and causing performance degradation. To solve this problem, the thesis focuses on developing advanced DPWM techniques that ensure effective cluster voltage control, even under severe grid imbalances, while simultaneously optimizing other control objectives, such as minimizing switching loss. The thesis first identifies a suitable DPWM method for CHB StatComs and analyzes its advantages in terms of capacitance reduction, switching loss reduction, enlargement of the inductive operation range, and reduction of converter voltage total harmonic distortion. The DPWM is then enhanced by considering the possibility of clamping to the zero-voltage level, providing benefits such as lower ZSV magnitude requirements and further reduction in switching loss. Subsequently, the thesis formulates DPWM as a finite-set optimization problem, proposing different cost functions to optimize the control objectives. This finite-set optimization formulation enables the embedding of cluster voltage control into DPWM implementation using model predictive control approaches, significantly enhancing the dynamical performance of CHB StatCom. The thesis evaluates the impact of the proposed DPWM methods on capacitor lifetime, highlighting the tradeoff between switching loss minimization and capacitor lifetime maximization. Finally, the thesis suggests future research directions, such as exploring increased clamping possibilities by considering the option of clamping to intermediate voltage levels. This novel concept has the potential to optimally address the aforementioned tradeoff between capacitor lifetime and converter switching loss. The thesis offers significant contributions to the field by effectively decoupling DPWM implementation from CHB StatCom cluster voltage control, making DPWM a feasible and reliable solution for next-generation CHB StatCom applications. Additionally, it introduces advanced DPWM strategies that allows the optimization of dedicated control objectives. Case studies demonstrate significant improvements when different control objectives are prioritized, such as a reduction of more than 45% in switching loss, an increase of over 10% in capacitor lifetime, an expansion of more than 50% in the inductive operation range, and a decrease of over 20% in dc capacitor capacitance compared to conventional sinusoidal pulsewidth modulation. The study of the thesis represents a crucial step towards fully leveraging the potential benefits of intelligently utilizing ZSV in CHB StatComs, thereby advancing CHB StatComs with improved reliability and efficiency performance. The findings presented in this thesis can benefit the design and operation of CHB StatComs, as well as other power system applications.

The conventional UPFC (Unified Power Flow Controller) is the most versatile equipment based on three-phase converters for controlling power flow in electric systems. This paper presents a UPFC with new and simple structures for voltage control (based on single-converters). It is shown that the voltage at a given point may be controlled in a simple way. In the first case, for each phase, one single-phase VSC (Voltage Source Converter) is connected in series with the system imposing the voltage, which has controlled magnitude and phase. This VSC is connected in “back-to-back” to another VSC, which is connected in parallel with the line. In the second case, the VSCs connected in series with the line are connected in back-to-back to three-phase VSC through a common DC link. Simulations were carried out using PSCAD/EMTDC to demonstrate that these UPFC configurations allow easy voltage control at a given point of the circuit using VSCs with smaller rating than using STATCOM.

Single-phase Voltage Source Converters (VSC) are required to handle significant second harmonic ripple current caused by the mismatch between instantaneous input and output power. Different passive and active filters are employed for protecting sensitive loads and sources, e.g., battery, photovoltaic (PV) cell, etc. from large ripple current. Tuned $LC$ filter is one of the well-accepted filtering solutions for single-phase VSCs as it significantly reduces the capacitance requirement compared to a capacitive filter. The better filter performance and enhanced reliability without addition of any active component make it suitable for low-cost applications. However, the choice of inductance ( $L$ ) and capacitance ( $C$ ) in $LC$ tuned filter is not unique and often decided by the desired $Q$ factor, which, in turn, shapes the filter characteristics in the passband region. This paper proposes a cost minimized selection procedure of $L$ and $C$ for the tuned filter in single-phase VSC. The cost study has been carried out considering the film capacitor and laminated steel inductor. The objective function for optimization is generalized to include volume and impedance characteristics of the filter. The cost optimized design of the $LC$ filter is compared with the capacitive filter with respect to steady-state and transient performances.

Recently, The necessity of renewable energy be on the rise in as fossil fuel is depleted. Study of offshore wind power generation is being carried out as part of the renewable energy business. The 3-level inverter for use in the offshore wind power system studied is increasing as high capacity about offshore wind power. The 3-level inverter had an advantage that make reference voltage higher than 2-level reference voltage. Also, study of the 3-phase inverter has increased nowadays. However, 3-level NPC (Neutral-Point-Clamped) inverter, two capacitors and the neutral point are connected in series, it can lead to problems reduces stability of the system and unbalance voltage. It is SVPWM (Space Vector Pulse Width Modulation) method. Because DPWM (Discontinuous Pulse Width Modulation) method didn't neutral point control as same method from SVPWM, each DPWM method need a method of neutral point control. This paper proposed a method of applying the offset voltage attem pts to resolve the difficulties of the neutral point voltage control. The equation for the offset voltage to be applied to the system of each DPWM was determined. The proposed method is implemented by comparison of block diagram. The proposed algorithm is verified by the simulation.

This paper presents a unified carrier-based modulation method for direct matrix converter. Various types of pulse width modulation (PWM) methods are generated by using the offset voltage, changing slope of carrier waveform, and adjusting the free parameters in the modulation algorithm. The proposed method is equivalent to the space vector pulse width modulation (SVPWM) for two-level and three-level voltage source inverter (VSI). This paper also presents a new viewpoint to understand the matrix converter modulation method such as single carrier based modulation technique for two-level VSI and double carrier based modulation technique for three-level VSI. Using the proposed method, this paper presents discontinuous pulse width modulation (DPWM) for the matrix converter. Therefore, a unified simple algorithm suitable for the digital implementation of all continuous and discontinuous PWM strategies is proposed. The feasibility of the proposed modulation method has been verified by a computer simulation results. These results show that the proposed carrier-based modulation method can be implemented easily without any tables.

Two generalized discontinuous carrier-based pulse-width modulation (GDPWM) methodologies for three-phase current source converters (CSC) are developed based on the classical space vector method and the carrier-based generalized discontinuous modulation scheme for voltage source converters (VSC). With feasible operation in both the linear and overmodulation regions, they provide the known advantages of the discontinuous carrier-based modulation in voltage source converters-reduced switching loss and reduced effective switching frequency especially in the overmodulation region. These modulation schemes are implemented for a current source inverter from which experimental results are presented to verify concepts and theory.

In order to meet the high performance and efficiency requirements, a new space vector-based discontinuous modulation strategy for neutral-point clamped three-level inverter is presented in this paper. Different from the conventional discontinuous PWM (DPWM) strategies, a new clamping state is applied to synthesize the reference voltage under the condition of low modulation index. The rms value of output current ripple for different clamping states are calculated, and then the distribution of the new clamping state and the other two clamping states adopted in conventional DPWMs is optimized based on the calculation results. The switching sequences are redesigned according to the new distribution of the three clamping states. The output voltage and current, switching loss, neutral-point voltage ripple and the common mode voltage of the proposed DPWM strategy and DPWM0–DPWM3 are compared by simulation and experimental results. The results show that by the use of the proposed strategy, the values of total demand distortion of output current ( I TDD) and weighted total harmonic distortion of output voltage $({\boldsymbol{V}_{{\mathbf{WTHD}}}})$ are the lowest. Furthermore, the product of switching loss and $I_{\rm TDD}$ of the proposed strategy maintains the lowest within a large range of modulation index-load angle plane. It can be concluded that the utilization of the new clamping state and optimal distribution of different clamping states could enhance the output performance of the inverter. Moreover, the high-efficiency requirement can also be realized at the same time.

Aiming at the performance of frequent and severe variation of electric traction load, a predicted control scheme of single phase active power filter (APF) based on the instantaneous reactive power theory and extrapolation algorithm is proposed in this paper. By predicting the fundamental component of traction load current pouring into the electric grid, to control the outage current of APF to compensate the harmonic currents produced by the traction load. The simulation to the proposed scheme by using the PSCAD/EMTDC simulation package is carried out, and the comparison to the conventional harmonic detecting methods under different conditions is presented. The simulation results show that the strategy proposed in the paper has little detecting errors, and the time delay of APF is greatly reduced.

This paper proposes bidirectional power flow control of a grid interactive solar photovoltaic (PV)-fed water pumping system. A brushless DC (BLDC) motor drive without phase current sensors is used to run a water pump. This system enables a consumer to operate the water pump at its full capacity for 24 hours regardless of the climatic condition and to feed a single-phase utility grid when water pumping is not required. The full utilization of a PV array and motor pump is made possible in addition to an enhanced reliability of the pumping system. A single-phase voltage source converter with a unit vector template generation technique accomplishes a bidirectional power flow control between the grid and the dc bus of the voltage source inverter (VSI), which feeds a BLDC motor. The VSI is operated at fundamental frequency, which minimizes the switching loss. The maximum power point operation of a PV array, and power quality improvements, such as power factor correction and reduction of total harmonic distortion of grid, are achieved in this system. Its applicability and reliability are demonstrated by various simulated results using MATLAB/Simulink platform and hardware implementation.

In this paper a fast dynamic response single phase active power filter is proposed. The method proposed, compensates the non-linear load by improving the power factor to the desired value and also eliminates the harmonics. The scheme is shown to work for both types compensation i.e. power factor correction plus harmonic elimination and harmonic elimination only under sinusoidal and non-sinusoidal supply voltage conditions. The active power filter (compensator) is realized using a single-phase voltage source inverter operated in a hysteresis current control mode. The method is validated through digital simulation results using MATLAB. The results have been shown with ideal and practical compensator with an emphasis on dynamic performance.

This paper presents Parallel Voltage Sourced Inverters to improve the efficiency in high current applications. Generally when two inverters are paralleled, they have unmatching currents flowing between them and to reduce that, we go for inductors. These inductors reduces the circulating currents flowing between the inverters and these currents are produced by common mode voltage differences between the output terminals of the two inverters. Standard Discontinuous PWM techniques when applied to parallel connected inverters with three separate inductors naturally produce high frequency common mode voltage differences. So an Interleaved Discontinuous PWM scheme along with sinusoidal reference is proposed to eliminate these voltage differences in parallel connected inverters. By using this technique, a three phase parallel inverter can be operated using a single three limb coupled inductor instead of three separate inductors. And this significantly reduces the high frequency differential current ripple and improves the efficiency of the system. Analysis are done for common mode voltage differences and for the common mode circulating currents using the above mentioned two techniques and it is shown that the common mode circulating currents (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</sub> ) and the common mode voltage differences (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm)</sub> are reduced by using Interleaved Discontinuous PWM technique. This is fed to an Induction motor load and the output currents are sinusoidal with less current ripples. Computer simulations are done using PSIM for Standard Discontinuous PWM and for Interleaved Discontinuous PWM and their respective waveforms are compared and it is shown that Interleaved Discontinuous PWM is efficient.

Model predictive control for single phase active power filter using modified packed U-cell (MPUC5) converter

This paper presents a novel architecture for a unit-delay digital deadbeat current controller for a shunt active power filter (APF). The APF is based on a fixed frequency pulsewidth modulated voltage-sourced converter (VSC). The proposed controller increases the APF current-tracking bandwidth without increasing the VSC switching frequency. Previous APF digital deadbeat controllers have a current-tracking delay of two or more sample-periods. One delay is due to current controller computation, a second sample delay represents VSC actuation time. The paper presents a new controller architecture employing both asynchronous programmable logic and a small microprocessor. Current-tracking feedback control calculations are executed in asynchronous programmable logic to effectively eliminate the controller computation delay. The microprocessor executes fundamental frequency disturbance rejection computations and all other supervisory functions. The proposed architecture retains all high-level functions in the microprocessor to minimize controller development time without compromising APF performance.

Now a days, because of enhancement in high speed computing elements, high voltage controlled semi-conductor devices and emergence of new power circuit topologies, the Voltage Source Converter (VSC) based Active Power Filter (APF) is finding applications for compensating harmonic currents drawn by the various loads. As the active filter consists of semi-conductor devices alone, the response time of this device is very fast and it doesn’t suffer from resonance and other stability problems as faced by the normal passive filters. The Active filters are generally used at harmonic producing loads. Among all APF’s the Shunt Active Power Filter (SAPF) is more prominent at medium/high voltage applications, and also it provides higher efficiency. SAPF in the power circuit can be used either by using the voltage-sourced PWM converter equipped with a DC capacitor or a current-sourced PWM converter equipped with a DC inductor. This paper presents an approach to determine reference compensation currents of the three-phase SAPF under distorted and/or unbalanced source voltages in steady state. It is planned to design a Synchronous Reference Frame (SRF) controller for Voltage Source Converter (VSC) based Shunt active power filter for harmonic compensation. The simulation results have been obtained by using MATLAB/ SIMULINK.