Investigation on the relationship between CD and CDU in memory devices

Critical Dimension (CD) Uniformity is one of the necessary parameters to assure good performance and reliable functionality of any integrated circuit (IC), and towards the advanced technology node 28nm and beyond, corresponding CD Uniformity becomes more and more crucial. It is found that bad mask CD Uniformity is a significant error source at 28nm process. The CD Uniformity on mask, if not controlled well, will badly impact wafer CD performance, and it has been well-studied that CD Uniformity issue from gate line-width in transistors would affect the device performance directly. In this paper we present a novel solution for mask global CD uniformity error correction, which is called as global loading effect correction (GLEC) method and applied nesting in the mask exposure map during the electron beam exposure. There are factors such as global chip layout, writing sequence and chip pattern density distribution (Global Loading), that work on the whole mask CD Uniformity, especially Global Loading is the key factor related to mask global CD error. From our experimental results, different pattern density distribution on mask significantly influenced the final mask CD Uniformity: the mask with undulating pattern density distribution provides much worse CD Uniformity than that with uniform one. Therefore, a GLEC model based on pattern density has been created to compensate the global error during the electron beam exposure, which has been proved to be efficacious to improve mask global CD Uniformity performance. Furthermore, it ’s also revealed that pattern type is another important impact factor, and GLEC coefficient need be modified due to the specific pattern type (e.g. dense line-space only, iso-space only or an average of them) to improve the corresponding mask CD uniformity.

Extreme ultraviolet lithography (EUVL) is getting closer to practical use for mass production every year. For applying EUV lithography to manufacturing, productivity improvement is a critical challenge. Throughput and yield are important factors for productivity. EUV source power is steadily advancing year by year, bringing improvements in throughput. Furthermore, yield improvement is necessary for productivity enhancement. In order to improve the yield in EUV lithography processing, further improvement of defectivity and critical dimension (CD) uniformity is required. Reduction of residue and in-film particle defects is very crucial work to enhance the productivity. For residue defects, it is found that the residue defects detected after development inspection (ADI) are perfectly transferred to after etching inspection (AEI), meaning that high defectivity of residue deteriorates yield directly. Furthermore, in-film particle defect counts increase from ADI to AEI because particles included in spin-on-carbon (SOC) and spin-on-glass (SOG) as well as that in resist film are the sources of defects in AEI, while particles mainly included in resist film can be observed in ADI. Figure 1 shows the normalized defectivity comparison between conventional rinse and filtration used and optimizing rinse used and improving filtration efficiency in ADI and AEI. ADI defectivity in which optimized rinse is applied and improving filtration efficiency achieved 0.04, while that in which conventional rinse and filtration are used defined 1.00, meaning the 96 % of improvement. In addition, AEI defectivity by using optimized rinse and improving of filtration efficiency shows 86 % of reduction as compared with that using conventional rinse and filtration. These results reveal that our novel actions for rinse and material supply show excellent performance for defect reduction. For the other aspect of yield improvement, CD uniformity control is one of the crucial factors. CD variations are comprised of several components such as wafer to wafer CD uniformity, field to field CD uniformity. To achieve CD uniformity target for manufacturing, we have optimized developing process with the latest technology. Then, 15 % of field to field CD uniformity improvement and significant improvement of wafer to wafer CD uniformity are achieved.

With the development of the lithography, the demand for critical dimension (CD) and CD uniformity (CDU) has reached a new level, which is harder and harder to achieve. There exists reflection at the interface between photo-resist and substrate during lithography exposure. This reflection has negative impact on CD and CDU control. It is possible to optimize the litho stack and film stack thickness on different lithography conditions. With the optimized stack, the total reflectivity for all incident angles at the interface can be controlled less than 0.5%, ideally 0.1%, which enhances process window (PW) most of the time. The theoretical results are verified by the experiment results from foundry, which helps the foundry achieve the mass production finally.

Critical dimension (CD) uniformity performance has improved significantly over the years by optimizing postbaking and development steps. As we continue to improve CD uniformity with PBS, our focus has shifted to other steps in the process. The crossover step, the point in the process where both develop and rinse are introduced simultaneously, has often been thought to have little or no effect on the develop time or to influence the uniformity results. However, careful examination of this step has determined that the crossover time, spin speed, and concentration of the develop/rinse mixture can have a significant effect on CD uniformity. Reduction of the typical radial effect was noted. Several design of experiment projects were run to examine these variables. A screening experiment was first run to determine the significant variables and their influence on uniformity. An optimization run was then made on crossover conditions, which included examination of plates from several vendors. Repeatability and sensitivity of the process to other variables were also determined. Results and recommendations are presented in this paper.

As optical lithography will be extended to device generations below 150 nm of design rule, the critical dimension (CD) uniformity on a photomask is required to be as small as 13 nm (3(sigma) ). The relationship between development method and dark erosion is discussed in view of CD variations. The temperature variation on a photomask is found to be more than 4 degrees Celsius for a conventional spin-spray development. An optimized process using a 'puddle process' to minimize developer temperature effect and non-uniform spray pressure effect on CD variation. The CD uniformity using the optimized process brings 11 nm in 3(sigma) over 127 mm X 127 mm area on a 6-inch mask.

In advanced CMOS technology node, the dummy gate critical dimension (CD) and its line head to head (HTH) space CD will directly affect the device performance and its long term reliability. Macro- and micro-uniformity of dummy gate CD and its HTH CD are key parameters for wafer yield and product quality. In dummy gate process, both the thickness uniformity of film stack (silicon nitride, amorphous carbon and etc.) and the CD uniformity (CDU) of lithography line will influence final dummy gate CDU. Feed forward APC mode for dummy gate CDU improvement requests a long term work in semiconductor manufacturing which is not a focus point here. In this paper, an advanced temperature compensation function of a commercial inductively coupled plasma (ICP) etcher will be mentioned. At the same time, both dummy gate and HTH CDU tuning by this function with feedback mode will be introduced. Some possible enhanced solutions of CDU improvement will also be addressed in this paper.

As the design rule of lithography becomes smaller, accuracy and precision in Critical Dimension (CD) and controllability of pattern-shape are required in semiconductor production. Critical Dimension Scanning Electron Microscope (CD SEM) is an essential tool to confirm the quality of the mask such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in the case of extremely rounded region of arbitrary enclosed patterns, CD fluctuation depending on Region of Interest (ROI) is very serious problem in Mask CD control, so that it decreases the yield. In order to overcome this situation, we have been developing 2-dimensonal (2D) method with system makers and comparing CD performance between mask and wafer using enclosed arbitrary patterns. In this paper, we summarized the results of our evaluation that compare error budget between 1-dimensonal (1D) and 2D data using CD SEM and other optical metrology systems.

The Semiconductor Industry Association (SIA) has placed stringent requirements on Next GenerationLithography mask critical dimension (CD) control. A new chemically amplified (CA) positive resist,Shipley XP2040D was evaluated for mask making application. This resist exhibited an extraordinary postexposure bake (PEB) sensitivity, less than 0.6 nm/ C, along with a sub-50 nm resolution. The PEB stabilityin ambient was larger than 4.5 hours and the line-edge-roughness (LER) was less than 2.9 nm. 1. INTRODUCTION Critical dimension (CD) control and uniformity for a SCALPEL mask must be kept within 7 nm (3 ) inorder to meet the SIA Roadmap requirement for 70 nm NGL mask fabrication [1]. Chemically amplified(CA) resists have been considered for NGL mask patterning because of their high resolution, high electronexposure sensitivity and etch selectivity. However, CD variation due to the PEB sensitivity of CA resistcomplicates the mask making process and needs to be minimized.Previous Finite Element Analysis modeling indicates there are PEB temperature gradients across a 200 mmSCALPEL mask and within each membrane of the mask. The thermal variations are due to the combinedcomplex three-dimensional mask structure coupled with the thermal gradients associated with the bakechamber environment. These gradients were experimentally confirmed through the measurement of criticalfeatures across various membranes on the mask array. A CD uniformity of 8-10 nm for inter-membrane and4-7 nm for intra-membrane was observed using a CA negative-tone resist, NEB22[2]. This CD variationwas mainly attributed to the large PEB sensitivity of the resist ( ~8 nm/ C).In order to meet the 7 nm SIA mask budget, CD non-uniformity due to thermal variations must be reduced.One way to minimize the influence of this thermal effect is to use low PEB sensitivity resists. This paperreports on the performance of Shipley XP2040D positive CA resist for 200 mm SCALPEL maskfabrication using the Leica VB6HR 100 KeV e-beam exposure system.

For sub half-micron lithography, control of the Critical Dimension, represents the key to a robust and manufacturable process. The lithographer must understand and tune the exposure system for critical dimension performance using variables such as Numerical Aperture (NA), Partial Coherence (PC), position of the Focal Plane. Exposure tool must be characterized for its lens signature and the tools must be matched for their CD variation within the optical field In a previous study, we demonstrated that the phase-shift focal plane monitor, PSFM accurately measures focal plane variations when appropriate calibrations are employed. That paper also described the development of a model to determine lens classic aberrations such as Coma, Astigmatism and Field Curvature. The publication correlated the results to an approximation of the stepper's Critical Dimension (CD) behavior for a matrix of NA and PC settings. The present study, continues to study CD uniformity through examination of the lens aberrations and field focal signature of optical steppers in a 0.35 um process. We describe a method of measuring the uniformity of numerical aperture (NA) and partial coherence (PC) across the exposure field this new tool is then applied as an aid in optical lens characterization and tool-to-tool matching. The information gathered is thereupon applied to measure lens aberrations and predict CD variation across the field under various settings of the lens focal plane, the predictions are validated by a comparison against CD uniformity as measured by an advanced critical dimension metrology system.

As critical dimension (CD) control requirements increase and process windows decrease, it is now of even higher importance to be able to determine and separate the sources of CD error in an immersion cluster, in order to correct for them. It has already been reported that the CD error contributors can be attributed to two primary lithographic parameters: effective dose and focus. In this paper, we demonstrate a method to extract effective dose and focus, based on diffraction based optical metrology (scatterometry). A physical model is used to describe the CD variations of a target with controlled focus and dose offsets. This calibrated model enables the extraction of effective dose and focus fingerprints across wafer and across scanner exposure field. We will show how to optimize the target design and the process conditions, in order to achieve an accurate and precise de-convolution over a larger range of focus and dose than the expected variation of the cluster. This technique is implemented on an ASML XT:1900Gi scanner interfaced with a Sokudo RF^3S track. The systematic focus and dose fingerprints obtained by this de-convolution technique enable identification of the specific contributions of the track, scanner and reticle. Finally, specific corrections are applied to compensate for these systematic CD variations and a significant improvement in CD uniformity is demonstrated.

Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like “middle side lobe measurement”, evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology process layers (poly-, active-, contact-, 1X-metal-, 2X-via layers). Referring to the correlation between wafer and reticle MTT, the contribution of the reticle CD-difference to the wafer CD-difference can be used as an evaluation method for the transfer-process of different mask sites.

As design rule shrinks down continuously, various technology have been developed to extend the resolution limits of lithography. One of those is Double Exposure Technology(DET). This paper is about not only resolution improvement but also Critical Dimension(CD) variation reduction with DET. As the design rule shrinks below 100nm, the core/peripheral area where we used to think we had sufficient margin is becoming the bottle neck for device fabrication. In this paper, in order to compare optimized single exposure (cell focus) and DET (cell, core/peripheral focus) for critical dimension uniformity(CDU) on cell and core/peripheral area, CDU was measured from wafer by use of simulation and measurement. Gate layer of DRAM device was used for the experiment. Exposure condition for the single exposure was set to crosspole and for DET, dipole and conventional respectively. Optical proximity correction(OPC) was done with in-house simulation tool on stiching area of the double exposure experiment. Same exposure tool and same process condition were used for each experiment and only the exposure condition was changed to compare local CDU, intra-field CDU, wafer CDU to find out how much CD variation can be reduced.

Double patterning technology overlay errors result in critical dimension (CD) distortions, and CD nonuniformity leads to overlay errors, demanding increased critical dimension uniformity (CDU) and improved overlay control. Scatterometry techniques are used to characterize the CD uniformity, focus, and dose control. We present CDU and profile characterization for spacer double patterning structures by advanced scatterometry methods. Our results include normal incidence spectroscopic reflectometry (NISR) and spectroscopic ellipsometry (SE) characterization of CDU sensitivity in spacer double patterning stacks. We further show the results of spacer DP structures by NISR and SE measurements. Metrology comparisons at various process steps including litho, etch, and spacer, and validation of CDU and profile, are all benchmarked against traditional critical dimension scanning electron microscope measurements.

As critical-dimension (CD) shrink below 0.18um, CD control becomes a major concern. Normally there are four approaches to improve CD control: to improve intra-field, intra-wafer, inter-wafer and inter-lot CD uniformity. In this paper, we propose a simple method to improve intra-wafer CD uniformity by optimize developing recipe. In DUV photolithography, intra-wafer CD variation is the major contributor to the overall CD variations. However there are many factors that may impact intra-wafer CD uniformity: Photoresist thickness uniformity, PEB uniformity, wafer surface roughness, substrate reflectivity and developing uniformity, so the situation become very complicated. In our studies, we tried to focus mainly on the developing uniformity of DUV process. To isolate the impact of developing method from other process factors, we proposed a simple method to check developing rate (Rmin) uniformity by photoresist thickness measurement. With this method, we had save a lot of time and manpower in developing recipe tuning and also had a deeper understanding of developing process of DUV resist.

As the microelectronics industry strives to achieve smaller device design geometries, control of linewidth, or critical dimension (CD), becomes increasingly important. Currently, CD uniformity is controlled by exposing large numbers of samples for a fixed exposure time which is determined in advance by calibration techniques. This type of control does not accommodate variations in optical properties of the wafers that may occur during manufacturing. In this work, a relationship is demonstrated between the intensity of light diffracted from a latent image consisting of a periodic pattern in the undeveloped photoresist and the amount of energy absorbed by the resist material (the exposure dose). This relationship is used to simulate exposure dose control of photoresist on surfaces which have different optical properties chosen to represent surfaces typical of those found in operating process lines. Samples include a variety of photoresist materials and substrates with a wide variety of optical properties. The optical properties of the substrates were deliberately varied to determine the effect of these properties on CD (in the presence and absence of an exposure monitor) during lithography. It was observed that linewidth uniformity of the developed photoresist can be greatly improved when the intensity of diffracted light from the latent image is used to control the exposure dose. Diffraction from the latent image grating structures was modeled using rigorous coupled wave analysis. The modeling is used to predict the diffraction from a latent image as a function of the substrate optical properties and the parameters of the latent image (i.e., linewidth, sidewall angle). Good agreement is obtained between theoretical and experimental observations. Conversely, the inverse problem is solved in which the parameters of the diffracting structure (the latent image) are determined from a measurement of the diffracted power. Therefore, the diffracted power can be monitored for the purpose of determining when the latent image will produce the proper CD upon development.